
FS8S0765RC
12
Figure 5. The waveforms at the OLP and auto restart
3.3 Thermal Shutdown(TSD) : The SenseFET and the
control IC are built in one package. This makes it easy for
the control IC to detect the heat generation from the
SenseFET. When the temperature exceeds approximately
160
°C, the thermal shutdown operates.
4. Soft Start : During the initial start up, the sink current of
the internal error amp(Amp1) shown in the figure 2 remains
zero. During this period, the soft start capacitor, Css is
charged by the 0.9mA current source and the 50K resistor
from 5V voltage source and the feedback capacitor, Cfb is
charged by the 0.9mA current source and the 2uA current, as
shown in the figure 6. By choosing much bigger Css than
Cfb, the feedback voltage, Vfb is increased slowly forcing
the SenseFET current to increase slowly. After Vfb reaches
its steady state value, only the current through the 50K
resistor charges the Css exponentially. If the value of Css is
too large so the rising speed of Vfb is higher than that of the
soft start voltag, Vss, there is possibility that Vfb touches
7.5V, the over load detection level during the soft start
period. In order to avoid this phenomenon, it is recom-
mended that the value of Css should not exceed 100 times of
Cfb.
Figure 6. The circuit for the soft start
5. Synchronization : It is well known that the
synchronization method is the best way to eliminate the
screen noise of the CRT monitor. The switching frequency of
the FS8S0765RC can vary from 20 KHz to 150 KHz by an
external sync signal. The internal sync comparator detects
the sync signal and determines the SenseFET turn-on time.
During the high pulse of the sync comparator output
voltage, the SenseFET remains an off state. The SenseFET is
turned on at the negative edge of the sync comparator output
voltage. The reference voltage of the sync
comparator is an inverted sawtooth with the base frequency
of 20kHz and with the varying range between 5.8V and 7.2V,
as shown in the figure 7 and figure 8. The inverted sawtooth
reference gets rid of the excessive switching noise at the very
first synchronized turn-on. The external sync signal is rec-
ommended to have an amplitude of minimum, 4.2V.
Figure 7. The circuit for the synchronization with external
sync
Figure 8. The waveforms at the synchronization.
6. Sync detector and burst operation : At the power saving
mode(off mode), the FS8S0765RC reduces the output volt-
ages to almost half of the normal value and enters into the
burst mode in order to make the power dissipation minimize.
The FS8S0765RC enters the power saving mode when the
voltage on pin #5(Vss) is higher than 3V, there is no sync
time
V
15V
9V
Vcc
Vds
Over load protection
Auto restart
time
V
7.5V
Vfb
22V
GATE
DRIVER
OSC
4
Voffset
2.5R
R
PWM
COMP.
2uA
0.9mA
Cfb
D
S
5
Vref
FS8S0765RC
50K
Css
Rss
D3
GATE
DRIVER
OSC
4
Voffset
2.5R
R
PWMCOMP.
2uA
0.9mA
Cfb
D
S
5
Vref
Css
Rss
D3
FS8S0765RC
5
SYNCCOMP.
7.2V
5.8V
External
Sync
5.8V
7.2V
Sync threshold
External Sync
CLK
5V