參數(shù)資料
型號(hào): FSA2567UMX
廠商: Fairchild Semiconductor
文件頁數(shù): 8/12頁
文件大?。?/td> 0K
描述: IC SWITCH 4PDT 16UMLP
標(biāo)準(zhǔn)包裝: 5,000
功能: 開關(guān)
電路: 1 x 4PDT
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.65 V ~ 4.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-UMLP
供應(yīng)商設(shè)備封裝: 16-UMLP(1.8x2.6)
包裝: 帶卷 (TR)
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA2567 Rev. 1.0.3
5
FS
A2
567
Low
-Power,
Dua
l
SIM
Ca
rd
Analog
Swit
ch
AC Electrical Characteristics
All typical value are for VCC=3.3V at 25°C unless otherwise specified.
Symbol
Parameter
Conditions
VCC (V)
TA=- 40C to +85C
Units
Min.
Typ.
Max.
tOND
Turn-On Time
Sel to Output
(DAT,CLK,RST)
RL = 50, CL = 35pF
VSW = 1.5V
65
95
ns
2.7 to 3.6
42
60
ns
tOFFD
Turn-Off Time
Sel to Output
(DAT,CLK,RST)
RL = 50, CL= 35pF
VSW = 1.5V
30
50
ns
2.7 to 3.6
20
40
ns
tONV
Turn-On Time
Sel to Output (VSIM)
RL = 50, CL = 35pF
VSW = 1.5V
55
80
ns
2.7 to 3.6
35
55
ns
tOFFV
Turn-Off Time
Sel to Output (VSIM)
RL = 50, CL = 35pF
VSW = 1.5V
35
50
2.7 to 3.6
22
40
ns
tPD
Propagation Delay
(DAT,CLK,RST)
CL = 35 pF, RL = 50
3.3
0.25
ns
tBBMD
Break-Before-Make
(DAT,CLK,RST)
RL = 50, CL = 35pF
VSW1 = VSW2 = 1.5V
2.7 to 3.6
3
18
ns
tBBMV
Break-Before-Make
(VSIM)
RL = 50, CL = 35pF
VSW1 = VSW2 = 1.5V
2.7 to 3.6
3
12
ns
Q
Charge Injection
(DAT,CLK,RST)
CL = 50pF, RGEN = 0 ,
VGEN = 0V
2.7 to 3.6
10
pC
OIRR
Off Isolation
(DAT,CLK,RST)
RL = 50, f = 10MHz
2.7 to 3.6
-60
dB
Xtalk
Non-Adjacent Channel
Crosstalk
(DAT,CLK,RST)
RL = 50, f = 10MHz
2.7 to 3.6
-60
dB
BW
-3db Bandwidth
(DAT,CLK,RST)
RL = 50, CL = 5pF
2.7 to 3.6
475
MHz
Note:
5.
Guaranteed by characterization.
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