參數(shù)資料
型號(hào): FSA3157
廠商: Fairchild Semiconductor Corporation
英文描述: TinyLogic Low Voltage UHS SPDT Analog Switch or 2:1 Multiplexer/Demultiplexer Bus Switch
中文描述: 微型邏輯低電壓超高強(qiáng)SPDT模擬開關(guān)或2:1多路復(fù)用器/解復(fù)用器總線開關(guān)
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 133K
代理商: FSA3157
www.fairchildsemi.com
4
N
DC Electrical Characteristics
(Continued)
Note 4:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B Ports).
Note 5:
Parameter is characterized but not tested in production.
Note 6:
R
ON
=
R
ON
max
R
ON
min measured at identical V
CC
, temperature and voltage levels.
Note 7:
Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions.
Note 8:
Guaranteed by Design.
AC Electrical Characteristics
Note 9:
Guaranteed by Design.
Note 10:
This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resis-
tance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Note 11:
Off Isolation
=
20 log
10
[V
A
/ V
Bn
]
Symbol
Parameter
V
CC
(V)
5.0
3.3
T
A
=
+
25
°
C
Typ
6
12
T
A
=
40
°
C to
+
85
°
C
Min
Units
Conditions
Min
Max
Max
R
flat
On Resistance Flatness
(Note 4)(Note 5)(Note 7)
I
A
=
30 mA, 0
V
Bn
V
CC
I
A
=
24 mA, 0
V
Bn
V
CC
I
A
=
8 mA, 0
V
Bn
V
CC
I
A
=
4 mA, 0
V
Bn
V
CC
2.5
1.8
28
125
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
°
C
Typ
T
A
=
40
°
C to
+
85
°
C
Min
Units
Conditions
Figure
Min
Max
3.5
Max
3.5
Number
t
PHL
t
PLH
Propagation Delay
1.65
1.95
2.3
2.7
3.0
3.6
4.5
5.5
1.65
1.95
2.3
2.7
3.0
3.6
4.5
5.5
1.65
1.95
2.3
2.7
3.0
3.6
4.5
5.5
ns
V
I
=
OPEN
Figures
1, 2
Bus to Bus
(Note 10)
1.2
0.8
0.3
1.2
0.8
0.3
t
PZL
t
PZH
Output Enable Time
Turn on Time
(A to B
n
)
7
23
13
6.9
7
24
14
7.6
ns
Figures
1, 2
3.5
2.5
3.5
2.5
V
I
=
2 x V
CC
for t
PZL
V
I
=
0V for t
PZH
1.7
3
2
5.2
12.5
7
1.7
3
2
5.7
13
7.5
t
PLZ
t
PHZ
Output Disable Time
Turn Off Time
ns
Figures
1, 2
V
I
=
2 x V
CC
for t
PLZ
V
I
=
0V for t
PHZ
(A Port to B Port)
1.5
0.8
0.5
5
1.5
0.8
0.5
5.3
3.8
3.5
t
B-M
Break Before Make Time 1.65
1.95
(Note 9)
ns
Figure 3
2.3
2.7
3.0
3.6
4.5
5.5
5.0
3.3
1.65
5.5
0.5
0.5
0.5
0.5
0.5
0.5
Q
Charge Injection (Note 9)
7
3
pC
C
L
=
0.1 nF, V
GEN
=
0V
R
GEN
=
0
R
L
=
50
f
=
10MHz
R
L
=
50
f
=
10MHz
R
L
=
50
R
L
=
600
0.5 V
P-P
f
=
600 Hz to 20 KHz
Figure 4
OIRR
Off Isolation (Note 11)
57
dB
Figure 5
Xtalk
Crosstalk
1.65
5.5
54
dB
Figure 6
BW
THD
3dB Bandwidth
Total Harmonic Distortion
(Note 9)
1.65
5.5
250
MHz
Figure 9
5
.011
%
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