- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1921 > FSA321UMX (Fairchild Semiconductor)IC SWITCH MULTIMEDIA 10-UMLP PDF資料下載
參數(shù)資料
| 型號(hào)： | FSA321UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH MULTIMEDIA 10-UMLP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 功能： | 音頻，USB 開關(guān) |
| 電路： | 1 x DPDT |
| 導(dǎo)通狀態(tài)電阻： | 11 歐姆（USB），2.7 歐姆（音頻） |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 4.3 V |
| 電流 - 電源： | 500µA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-UFQFN |
| 供應(yīng)商設(shè)備封裝： | 10-uMLP（1.4x1.8） |
| 包裝： | 帶卷 (TR) |
Lattice Semiconductor
ispGDX2 Family Data Sheet
9
Table 3. ispGDX2 Supported I/O Standards
The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated
with a bank consistent with their location.
Table 4. I/O Standards Supported by Dedicated Inputs
For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design
and Usage Guidelines.
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feed-
back signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and
generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.
Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide
capabilities of the PLL, each PLL has associated dividers. The M divider is used to divide the clock signal, while the
sysIO Standard
Nominal VCCO
Nominal VREF
Nominal VTT
LVCMOS 3.3
3.3V
—
LVCMOS 2.5
2.5V
—
LVCMOS 1.8
1.8V
—
LVTTL
3.3V
—
PCI 3.3
3.3V
—
PCI -X
3.3V
—
AGP-1X
3.3V
—
SSTL3 class I & II
3.3V
1.5V
SSTL2 class I & II
2.5V
1.25V
CTT 3.3
3.3V
1.5V
CTT 2.5
2.5V
1.25V
HSTL class I
1.5V
0.75V
HSTL class III
1.5V
0.9V
0.75V
HSTL class IV
1.5V
0.9V
1.5V
GTL+
1.8/2.5/3.3V
1.0V
1.5V
LVPECL
1, 2, 3
3.3V
—
LVDS
2.5/3.3V
—
Bus-LVDS
2.5/3.3V
—
1. LVPECL drivers require three resistor pack (see Figure 17).
2. Depending on the driving LVPECL output specication, GDX2 LVPECL input driver may require terminating resistors.
3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines.
LVCMOS
LVDS
All other ASIC I/Os
Global OE Pins
Yes
No
Yes
2
Global MUX Select Pins
Yes
No
Yes
2
Resetb
Yes
No
Yes
2
Global Clock/Clock Enables
Yes
2
ispJTAG Port
Yes
1
No
TOE
Yes
No
1. LVCMOS as dened by the VCCJ pin voltage.
2. No PCI clamp.
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FSA3259BQX | IC SWITCH DUAL SP3T 16DQFN |
| FSA3357K8X | IC SWITCH SP3T US8 |
| FSA4157AL6X_F087 | IC SWITCH SPDT 6MICROPAK |
| FSA4159L6X_F113 | IC SWITCH SPDT 6MICROPAK |
| FSA5157L6X | IC SWITCH SPDT 6MICROPAK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FSA321UMX_F113 | 功能描述:多路器開關(guān) IC Multimedia & USB2 Hi-Speed & Aud Swtch RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| FSA3230 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:High-Speed USB2.0 / Mobile High- Definition Link (MHLa?￠) with Negative Swing Audio |
| FSA3230UMX | 功能描述:電源開關(guān) IC - USB HiSpeed USB 2.0 MHL w/Neg Swing Audio RoHS:否 制造商:Micrel 電源電壓-最小:2.7 V 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| FSA3259 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual SP3T Analog Switch |
| FSA3259BQX | 功能描述:模擬開關(guān) IC FINISHED GOOD RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。