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參數(shù)資料
| 型號(hào)： | FSA3357K8X |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SWITCH SP3T US8 |
| 產(chǎn)品變化通告： | Mold Compound Change 27/Aug/2008 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 開關(guān) |
| 電路： | 1 x SP3T |
| 導(dǎo)通狀態(tài)電阻： | 15 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFSOP（0.091"，2.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | US8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1219 (CN2011-ZH PDF) |
| 其它名稱： | FSA3357K8XDKR |
www.fairchildsemi.com
4
FSA
3
357
DC Electrical Characteristics (Continued)
Note 4: Measured by the voltage drop between A and Bn pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A
or Bn Ports).
Note 5: Parameter is characterized but not tested in production.
Note 6:
'RON = RON max RON min measured at identical VCC, temperature and voltage levels.
Note 7: Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions.
AC Electrical Characteristics
Note 8: This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and
the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Note 9: Guaranteed by Design.
Note 10: Off Isolation = 20 log10 [VA / VBn]
Capacitance (Note 11)
Note 11: TA = 25qC, f = 1 MHz, Capacitance is characterized but not tested in production.
Symbol
Parameter
VCC
TA = 25qCTA = 40qC to 85qC
Units
Conditions
Figure
(V)
Min
Typ
Max
Min
Max
Number
tPHL
Propagation Delay
1.65
1.95
2.0
ns
VI = OPEN
Figures
1, 2
tPLH
Bus to Bus
2.3
2.7
1.1
(Note 8)
3.0
3.6
0.7
4.5
5.5
0.4
tPZL
Output Enable Time
1.65
1.95
5.0
32.0
5.0
34.0
ns
Figures
1, 2
tPZH
Turn on Time
2.3
2.7
3.0
15.0
3.0
16.5
VI = 2 x VCC for tPZL
(A to Bn)3.0 3.6
2.0
9.5
2.0
11.0
VI = 0V for tPZH
4.5
5.5
1.5
6.5
1.5
7.0
tPLZ
Output Disable Time
1.65
1.95
3.0
14.0
3.0
14.5
ns
Figures
1, 2
tPHZ
Turn Off Time
2.3
2.7
2.0
7.2
2.0
7.8
VI = 2 x VCC for tPLZ
(A Port to Bn Port)
3.0
3.6
1.5
5.1
1.5
5.5
VI = 0V for tPHZ
4.5
5.5
0.8
3.7
0.8
4.0
tB-M
Break Before Make Time
1.65
1.95
0.5
ns
Figure 3
(Note 9)
2.3
2.7
0.5
3.0
3.6
0.5
4.5
5.5
0.5
Q
Charge Injection (Note 9)
5.0
3.0
pC
CL = 0.1 nF, VGEN = 0V
Figure 4
3.3
2.0
RGEN = 0:
OIRR
Off Isolation (Note 10)
1.65
5.5
58.0
dB
RL = 50:
Figure 5
f = 10MHz
Xtalk
Crosstalk
1.65
5.5
60.0
dB
RL = 50:
Figure 6
f = 10MHz
BW
3dB Bandwidth
1.65
5.5
250.0
MHz
RL = 50:
Figure 9
THD
Total Harmonic Distortion
5.0
.01
%
RL = 600:
(Note 9)
0.5 VP-P
f = 600 Hz to 20 KHz
Symbol
Parameter
Typ
Max
Units
Conditions
Figure
Number
CIN
Control Pin Input Capacitance
2.0
pF
VCC = 0V
CIO-B
B Port Off Capacitance
3.6
pF
VCC = 5.0V
Figure 7
CIOA-ON
A Port Capacitance When Switch Is Enabled
14.5
pF
VCC = 5.0V
Figure 8
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