參數(shù)資料
型號: FSA9288AUMX
廠商: Fairchild Semiconductor
文件頁數(shù): 28/30頁
文件大?。?/td> 0K
描述: IC USB MULTIMEDIA SWITCH 20-UMLP
標(biāo)準(zhǔn)包裝: 5,000
功能: USB 開關(guān)
電路: 3:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 4.4 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-UFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-UMLP(4x3)
包裝: 帶卷 (TR)
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A Rev 1.1.0
7
FS
A9
2
80A
US
B
Po
rt
Mu
lt
im
edia
Swi
tc
h
,
Fea
turi
n
g
Automatic
Se
lect
a
nd
Ac
ces
s
ory
Detection
3. I
2C
The FSA9280A integrates a fast-mode I
2C slave controller
compliant with the I
2C specification version 2.1 requirements.
The FSA9280A I
2C interface runs up to 400KHz.
The slave address is shown in Table 2. Status information
and configuration occurs via the I
2C interface.
Please see Section 9.7 for more information.
Table 2
– I
2C Slave Address
Name
Size (Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave Address
8
0
1
0
1
0
1
Read / Write
8bits
S
Slave
Address
WR
A
Register
Address K
A
Write
Data
A
Write
Data
K+1
A
Write
Data
K+2
A
Write
Data
K+N-1
A P
Note:
Single Byte write is initiated by Master with P immediately following first data byte.
Figure 4.
I
2C Write Sequence
Figure 5.
I
2C Read Sequence
Figure 6.
I
2C Reset Mode Timing
S
WR A
A S
RD A
A
NA P
Register address to Read specified
Note:
8bits
If Register is not specified Master will begin read from current register. In this case only sequence showing in Red
bracket is needed
Single or multi byte read executed from current register location (Single Byte read is
initiated by Master with NA immediately following first data byte)
Read Data K+1
Read Data K+N-1
8bits
Slave Address
Register Address K
Read Data K
Slave Address
From Master to Slave
S
Start Condition
NA NOT Acknowledge (SDA High)
RD
Read =1
From Slave to Master
A
Acknowledge (SDA Low)
WR Write=0
P
Stop Condition
VBAT
VDDIO
SDA
SCL
Internal Reset Time
30ms
400s
Idle Standby
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