FSES0765RG
13
exceed the rated voltage before the over load protection is
activated, resulting in the breakdown of the devices in the
secondary side. In order to prevent this situation, an over
voltage protection (OVP) circuit is employed. In general,
Vcc is proportional to the output voltage and the FPS uses
Vcc instead of directly monitoring the output voltage. If
V
CC
exceeds 19V, an OVP circuit is activated resulting in
the termination of the switching operation. In order to avoid
undesired activation of OVP during normal operation, Vcc
should be designed to be below 19V.
3.4 Thermal Shutdown (TSD) :
The Sense FET and the
control IC are built in one package. This makes it easy for
the control IC to detect the heat generation from the Sense
FET. When the temperature exceeds approximately 150
°
C,
the thermal shutdown is activated.
4. Synchronization
: Since the FSES0765RG is designed for
CRT Monitor applications, this device has a synchronization
function to minimize the screen noise. The MOSFET is
turned on being synchronized to the external synchronization
signal as shown in figure 9. In order to reduce voltage stress
on the secondary side rectifier, a double pulse prevention
function is included as well. The MOSFET’s turn-on is
inhibited for 5us after the MOSFET is turned off in order to
eliminate a double pulse situation.
Figure 9. Synchronization Operation
5. Soft Start
: The FPS has an internal soft start circuit that
slowly increases the PWM comparator’s inverting input
voltage together with the Sense FET current during startup.
The typical soft start time is 15ms. The pulse width to the
power switching device progressively increases to establish
the correct working conditions for transformers, inductors,
and capacitors. The voltage on the output capacitors also
progressively increases with the intention of smoothly
establishing the required output voltage. It also helps to
prevent transformer saturation and reduce the stress on the
secondary diode during startup.
6. Burst operation :
In order to minimize the power
consumption in the standby mode, the FSES0765RG
employs burst operation. Once FSES0765RG enters into
burst mode, effective switching frequency and all output
voltages are reduced. Figure 10 shows the typical feedback
circuit to force the FSES0765RG to enter burst operation. In
normal operation, the picture on signal is applied and the
transistor Q
1
is turned on, which de-couples R
3
and D1 from
the feedback network. Therefore, only V
o1
is regulated by
the feedback circuit in normal operation and determined by
R
1
and R
2
as
In standby mode, the picture on signal is disabled and the
transistor Q
1
is turned off, which couples R
3
and D
1
to the
reference pin of KA431. Then, the voltage on the reference
pin of KA431 is higher than 2.5V and the current through the
opto coupler increases, which increases the current through
the opto LED. This pulls down the feedback voltage (V
FB
)
of FPS and forces FPS to stop switching until Vcc drops to
8.5V. When Vcc reaches 8.5V, the FPS starts switching with
a switching frequency of 50kHz and a peak drain current of
0.6A until Vcc reaches 9V. When Vcc reaches 9V, the
switching operation is terminated again until Vcc reduces to
8.5V.
Figure 10. Typical feedback Circuit for FPS Burst
Operation
7.0V
6.0V
5us sync detect
blanking
Sync signal
Drain
Current
Current limit level determined by feedback voltage
Sync signal
7.0V
6.0V
MOSFET turn-off
MOSFET turn-On
5us sync detect
blanking
V
o1
norm
2.5
R
-------------------
R
2
+
R
2
=
Picture ON
Micom
Linear
Regulator
V
O2
V
O1
(B+)
KA431
R
2
R
1
R
3
R
bias
R
D
R
F
C
F
D
1
Q1
A
C
R