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參數(shù)資料
| 型號(hào)： | FSM6403MTC20X |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | LEAD FREE, MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 670K |
| 代理商： | FSM6403MTC20X |
2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6403 Rev. 1.0.4
10
FM
S6403
—
Triple
Video
D
rivers
wit
h
Select
able
H
D
/PS/SD
B
y
pass
Filt
ers
f
o
rR
G
B
and
YPbPr
Signals
Figure 16. Bi-level External Sync Clamping and Bias
HD and Bypass Mode Video Sync
Processing
When the input signal is a high-definition signal, the tri-
level sync pulse is too short to allow proper clamp
operation. Rather than clamp during the sync pulse, the
sync pulse is located and the signal is clamped to the
blanking level. This is done such that the sync tip is set
to approximately 250mV for signals with 300mV sync tip
amplitude. The EXT_SYNC control input selects the
sync stripper output or the SYNC_IN pin for use by the
clamp circuit.
Note
:
7.
The SYNC_IN timing for HD signals is different
from the timing for SD or PS signals.
For HD signals, the SYNC_IN signal must be high when
the clamp must be active. This is during the time
immediately after the sync pulse while the signal is at
the blanking level. This operation is shown in Figure 17.
Note that the following diagrams illustrate DC restore
functionality and indicate output voltage levels for both
0dB and 6dB gain (1VPP and 2VPP video signals at the
FMS6403 output pin). SYNC timings, T1 and T2, are
defined in the HD Electrical Specifications table section.
Figure 17. Tri-level Blanking Clamp
Note
:
8.
Tri-level sync may only be compressed 5%. If HD
sync is compressed more than 5%, it may not be
properly located.
Sync Timing
Normally, the FMS6403 responds to bi-level sync and
clamps the sync tip during period ‘B’ in Figure 19. When
the filters are switched to high-definition mode (30MHz)
or bypass mode, the sync processing responds to tri-
level sync and clamps to the blanking level during
period ‘C’ in Figure 19.
Note
:
9.
The diagram indicates SYNC timings at the output
pin.
Figure 18. Sync Timing Bi-level
Figure 19. Sync Timing Tri-level
The tri-level sync pulse is located such that the broad
pulses in the vertical interval do not trigger the clamp.
To improve the system settling at turn-on, the broad
pulses are clamped to just above ground. Once the
broad pulses (and tri-level sync tips) are above ground,
the normal clamping process takes over and clamps to
the blanking level during period ‘C’ in Figure 19.
FMS6403 is supports the video standards and
associated sync timings shown in Table 1, (additional
standards, such as 483p59.94, also work correctly).
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