參數(shù)資料
型號: FST16213
廠商: Fairchild Semiconductor Corporation
英文描述: 24-Bit Bus Exchange Switch(24位總線交換開關(guān))
中文描述: 24位總線交換開關(guān)(24位總線交換開關(guān))
文件頁數(shù): 4/6頁
文件大?。?/td> 153K
代理商: FST16213
www.fairchildsemi.com
4
F
AC Electrical Characteristics
Note 6:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 7)
Note 7:
T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note:
Input driven by 50
source terminated in 50
Note:
C
L
includes load and stray capacitance
Note:
Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C,
C
L
=
50pF, RU
=
RD
=
500
V
CC
=
4.5
5.5V
Min
Max
0.25
Units
Conditions
Figure No.
V
CC
=
4.0V
Min
Max
0.25
t
PHL
,t
PLH
Prop Delay Bus to Bus (Note 6)
ns
V
I
=
OPEN
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
t
PHL
,t
PLH
Prop Delay A1 to A2
0.5
0.5
ns
V
I
=
OPEN
t
PZH
, t
PZL
Output Enable Time, S to A or B
1.5
7.5
8.0
ns
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
t
PHZ
, t
PLZ
Output Disable Time S to A or B
1.0
8.5
9.0
ns
Figure 1
Figure 2
t
PZH
, t
PZL
Output Enable Time, S0 to A2 and B2
1.5
9.5
10.0
ns
Figure 1
Figure 2
t
PHZ
, t
PLZ
Output Disable Time, S0 to A2 and B2
1.5
9.0
10.0
ns
Figure 1
Figure 2
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
C
I/O
Control pin Input Capacitance
Input/Output Capacitance
3
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
S0, S1, or S2
=
GND
10
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