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參數(shù)資料
| 型號： | FSTUD32450GX |
| 英文描述： | BUS SWITCH|CMOS|BGA|114PIN|PLASTIC |
| 中文描述： | 總線開關(guān)|的CMOS | BGA封裝| 114PIN |塑料 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 474K |
| 代理商： | FSTUD32450GX |
2001 Fairchild Semiconductor Corporation
DS500447
www.fairchildsemi.com
August 2001
Revised August 2001
F
2
S
FSTUD32450
Configurable 4-Bit to 40-Bit Bus Switch with
2V Undershoot Protection and Selectable Level Shifting
General Description
The Fairchild Universal Bus Switch FSTUD32450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed
CMOS TTL-compatible bus switching. The low On Resis-
tance of the switch allows inputs to be connected to out-
puts without adding propagation delay or generating
additional ground bounce noise.
The FSTUD32450 is designed to allow “customer” configu-
ration control of the enable connections. The device can be
organized as either a ten 4-bit, eight 5-bit, four 10-bit, two
20-bit or one 40-bit enabled bus switch. Also achievable
are 8-bit and 16-bit enabled configurations (see Functional
Description). The device's bit configuration is controlled
through select pin logic. (see Truth Table). When OE
x
is
LOW, Port A
x
is connected to Port B
x
. When OE
x
is HIGH,
the switch is OPEN.
The A and B Ports are protected against undershoot to
support an extended range to 2.0V below ground.
Fairchild's integrated Undershoot
(UHC
) senses undershoot at the I/O, and responds by
preventing voltage differentials from developing and turn-
ing the switch on.
Another innovative device feature is the addition of a level
shifting select pin, “S
2
and S
5
”. When S
2
and S
5
are LOW,
the device behaves as a standard N-MOS switch. When S
2
and S
5
are HIGH, a diode to V
CC
is integrated into the cir-
cuit allowing for level shifting between 5V inputs and 3.3V
outputs.
Hardened
Circuit
Features
I
Undershoot protected to
2V (A and B Ports)
I
Voltage level shifting
I
4
switch connection between two ports
I
Minimal propagation delay through the switch
I
Low l
CC
I
Zero bounce in flow-through mode
I
Control inputs compatible with TTL level
I
See Applications Notes AN-5008 and AN-5021 for UHC
details
I
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Applications Note
Select pins S
0
, S
1
, S
2
, S
3
, S
4
and S
5
are intended to be
used as static user configurable control pins. The AC per-
formance of these pins has not been characterized or
tested. Switching of these select pins during system opera-
tion may temporarily disrupt output logic states and/or
enable pin controls.
40-bit configuration can be achieved by connecting the
OE
1
and the OE
6
pins to together.
Ordering Code:
Note 1:
BGA package available in Tape and Reel only.
UHC
is a trademark of Fairchild Semiconductor Corporation.
Order Number
FSTUD32450GX
(Note 1)
Package Number
BGA114A
Package Description
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
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