參數(shù)資料
型號(hào): FT2232HQ-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 3/67頁
文件大?。?/td> 0K
描述: IC USB HS DUAL UART/FIFO 64-QFN
標(biāo)準(zhǔn)包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點(diǎn): USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 4096 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 3 V ~ 3.6 V
帶并行端口:
帶自動(dòng)流量控制功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
其它名稱: 768-1025-6
Copyright 2012 Future Technology Devices International Limited
11
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
Pin No.
Name
Type
Description
2
OSCI
INPUT
Oscillator input.
3
OSCO
OUTPUT
Oscillator output.
6
REF
INPUT
Current reference – connect via a 12K resistor @ 1% to GND.
7
DM
INPUT
USB Data Signal Minus.
8
DP
INPUT
USB Data Signal Plus.
13
TEST
INPUT
IC test pin – for normal operation should be connected to GND.
14
RESET#
INPUT
Reset input (active low).
60
PWREN#
OUTPUT
Active low power-enable output.
PWREN# = 0: Normal operation.
PWREN# =1 : USB SUSPEND mode or device has not been configured.
This can be used by external circuitry to power down logic when device
is in USB suspend or has not been configured.
36
SUSPEND#
OUTPUT
Active low when USB is in suspend mode.
59
PWRSAV#
INPUT
USB Power Save input. This is an EEPROM configurable option used
when the FT2232H is used in a self powered mode and is used to
prevent forcing current down the USB lines when the host or hub is
powered off.
PWRSAV# = 1 : Normal Operation
PWRSAV# = 0 : FT2232H forced into SUSPEND mode.
PWRSAV# can be connected to GND (via a 10K resistor) and another
resistor (e.g. 4K7) connected to the VBUS of the USB connector. When
this input goes high, then it indicates to the FT2232H that it is
connected to a host PC. When the host or hub is powered down then
the FT2232H is held in SUSPEND mode.
Table 3.2 Common Function pins
Pin No.
Name
Type
Description
63
EECS
I/O
EEPROM – Chip Select. Tri-State during device reset.
62
EECLK
OUTPUT
Clock signal to EEPROM. Tri-State during device reset. When not in reset, this
outputs the EEPROM clock.
61
EEDATA
I/O
EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to Data-Out
of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM to VCC via
a 10K resistor for correct operation. Tri-State during device reset.
Table 3.3 EEPROM Interface Group
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