參數(shù)資料
型號(hào)： FT245RL-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù)： 4/37頁(yè)
文件大小： 0K
描述： IC USB TO PARALLEL FIFO 28-SSOP
產(chǎn)品培訓(xùn)模塊： USB Introduction
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： USB 至 FIFO 控制器
接口： USB，F(xiàn)IFO，（同步/異步）
電源電壓： 1.8 V ~ 5.25 V
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 標(biāo)準(zhǔn)包裝
安裝類(lèi)型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 634 (CN2011-ZH PDF)
配用： 768-1020-ND - MOD USB PARALLEL FIFO DEV FT245R
其它名稱(chēng)： 768-1011-6
Copyright 2010 Future Technology Devices International Limited
12
Document No.: FT_000052
FT245R USB FIFO IC Datasheet Version 2.12
Clearance No.: FTDI# 39
Pin
No.
Name
Type
Description
6
D5
I/O
FIFO Data Bus Bit 5
7
D6
I/O
FIFO Data Bus Bit 6
8
D3
I/O
FIFO Data Bus Bit 3
9
PWREN# Output
Goes low after the device is configured by USB, then high during USB
suspend. Can be used to control power to external logic P-Channel logic
level MOSFET switch. Enable the interface pull-down option when using the
PWREN# pin in this way. Should be pulled to VCCIO with 10kΩ resistors.
10
RD#
Input
Enables the current FIFO data byte from D0…D7 when low. Fetched the next
FIFO data byte (if available) from the receive FIFO buffer when RD# goes
from high to low. See Section 3.5 for timing diagram.
11
WR
Input
Writes the data from byte from D0...D7 pins into the transmit FIFO buffer
when WR goes from high to low. See section 3.6 for timing diagram.
21
TXE#
Output
When high, do not write data into the FIFO. When low, data can be written
into the FIFO by strobing WR high, then low. During reset this signal pin is
tri-state. See Section 3.6 for timing diagram.
22
RXF#
Output
When high, do not read data from the FIFO. When low, there is data
available in the FIFO which can be read by strobing RD# low, then high
again. During reset this signal pin is tri-state. See Section 3.5 for timing
diagram.
If the Remote Wakeup option is enabled in the internal EEPROM, during USB
suspend mode (PWREN# = 1) RXF# becomes an input. This can be used to
wake up the USB host from suspend mode by strobing this pin low for a
minimum of 20ms which will cause the device to request a resume on the
USB bus.
Table 3.8 FIFO Interface Group (see note 3)
Notes:
1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when
using the internal clock generator. Operation at +3.3V is possible using an external
crystal oscillator.
2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT245R,
please refer to Section 8.2
3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ
resistors. These pins can be programmed to gently pull low during USB suspend (
PWREN# = “1”) by setting an option in the internal EEPROM.
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