
FingerTIP
Infineon Technologies
21/38
FTF 1100 MF1 V2.0 databook 3.3 (05.00)
The third part of the recommended circuit is consists of the drivers and resistors between
the cable and the 21-pin sensor-connector. The resistors R1 and R4 are required for both
supply current limitation and ESD protection. The drivers in the data and ready lines
decouple these lines from the EPP port. The combination of driver and resistor in the
RESET and REQUEST line limits a possible supply current of the sensor via these I/O
pins. The values of R5 and R6 will be dependent on the maximum output current of the
drivers, so it is recommended to choose such a combination of driver and resistor such
that the maximum current per handshake line is < 5mA.
For stabilising the sensor power supply, capacitors C1 and C2 are required.
4 The Serial Interface SPI
This chapter describes the serial interface of the FingerTIP and how to read out an
image, change the dynamics and set sleep mode. First the basic interface information, the
data transfer protocol and electrical and timing parameters of the sensor's SPI mode are
described. Then the readout procedure is illustrated by a block diagram. Finally, the pinout
of the sensor's SPI mode is shown.
For further information to design-in the sensor, please refer to the Design-In Guideline /2/.
4.1 Basic Information on the Serial Interface SPI
The FingerTIP Serial Peripheral Interface (SPI) can be operated with a clock rate of up
to 5 MHz depending on the supply voltage (see table 7). Every command sent by the
master is confirmed with a response from the sensor. The on-chip SPI interface allows bus
protocols for the SPI modes (0,0) and (1,1). With the rising edge of the clock the SPI
interface reads data from the SI pin while the SPI interface outputs data on the SO pin with
the falling edge of the clock. The data format of the commands, the corresponding
responses and the image data is 8-bit with LSB first. The SPI interface is implemented as
a 3-line bus consisting of input, output and clock signals plus a chip-select line. This allows
Multi-Master and Slave operation with bus-compliant systems.