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參數(shù)資料
| 型號(hào)： | FTLX1441F2 |
| 元件分類(lèi)： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 1290-1330nm, 31875Mbps(Tx), 31875Mbps(Rx), SC CONNECTOR |
| 封裝： | ROHS COMPLIANT |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大小： | 336K |
| 代理商： | FTLX1441F2 |
FTLX1441 Product Specification – December 2007
I. PIN DESCRIPTION
Signal Name
Level
I/O
Pin No.
Description
Management and Monitoring Ports
MDIO
Open Drain
I/O
17
Management Data I/O. Requires
external 10 - 22 k pull-up to the
APS on host.
MDC
1.2 V
CMOS
I
18
Management Data Clock Input
PRTAD4
1.2 V
CMOS
1
19
Port Address Input bit 4
PRTAD3
1.2 V
CMOS
I
20
Port Address Input bit 3
PRTAD2
1.2 V
CMOS
I
21
Port Address Input bit 2
PRTAD1
1.2 V
CMOS
I
22
Port Address Input bit 1
PRTAD0
1.2 V
CMOS
I
23
Port Address Input bit 0
LASI
Open Drain
O
9
Link Alarm Status Interrupt Output.
Open Drain Compatible Output with
10 - 20 k pull-up on host.
Logic high = Normal Operation
Logic low = Status Flag Triggered
RESET
Open Drain
I
10
Reset Input.
Open Drain Compatible Input with
22 k pull-up to APS internal to
transponder.
Logic high = Normal Operation
Logic low = RESET
Vendor Specific
11,15,16,24
Vendor Specific Pins.
Leave unconnected when not used.
TX ON/OFF
Open Drain
I
12
TX ON/OFF Input.
Open Drain Compatible Input with
22 k pull-up to APS internal to
transponder.
Logic high = Transmitter On
Logic low = Transmitter Off
MOD DETECT
O
14
Pulled low inside transponder
through a 1 k resistor to Ground
Transmit Functions
Reserved
I
68
67
Reserved For Future Use
TX LANE 3–
TX LANE 3+
I
65
64
Module XAUI Input Lane 3–
Module XAUI Input Lane 3+
TX LANE 2–
TX LANE 2+
I
62
61
Module XAUI Input Lane 2–
Module XAUI Input Lane 2+
TX LANE 1–
TX LANE 1+
I
59
58
Module XAUI Input Lane 1–
Module XAUI Input Lane 1+
TX LANE 0–
TX LANE 0+
AC-coupled,
Internally biased
differential
XAUI
I
56
55
Module XAUI Input Lane 0–
Module XAUI Input Lane 0+
Finisar Corporation – December 2007 Rev. B
Page 2
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