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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 129/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
129
4.2.
Memory Shadowing
Any block of memory that can be designated as read only or write-only can be “shadowed” into GMCH
DRAM memory. Typically, this is done to allow ROM code to execute more rapidly out of main DRAM.
ROM is used as a read-only during the copy process while DRAM at the same time is designated write-
only. After copying, the DRAM is designated read-only so that ROM is shadowed. Processor bus
transactions are routed accordingly.
4.3.
I/O Address Space
The GMCH never responds to I/O cycles initiated on AGP.
The GMCH does not support the existence of any other I/O devices other than itself on the
processor bus. The GMCH generates either hub interface or AGP/PCI (if enabled) bus cycles for all
processor I/O accesses. If internal graphics is enabled, the GMCH routes the access to hub interface
or legacy I/O registers supported by the internal graphics device. The GMCH contains two internal
registers in the processor I/O space, Configuration Address Register (CONF_ADDR) and the
Configuration Data Register (CONF_DATA). These locations are used to implement PCI
configuration space access mechanism and as described in this document.
The processor allows 64K+3 bytes to be addressed within the I/O space. The GMCH propagates the
processor I/O address without any translation on to the destination bus and, therefore, provides
addressability for 64K+3 byte locations. Note that the upper 3 locations can be accessed only during
I/O address wrap-around when processor bus A16# address signal is asserted. A16# is asserted on
the processor bus when an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or
0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses, other than ones used for PCI configuration space access or ones that target the
internal graphics device (or AGP/PCI) are forwarded to the hub interface. The GMCH will not post
I/O write cycles to IDE. The PCICMD1 or PCICMD2 register can disable the routing of I/O cycles
to the AGP.
The GMCH never responds to I/O cycles initiated on AGP.
4.3.1.
GMCH Decode Rules and Cross-Bridge Address Mapping
The GMCH’s address map applies globally to accesses arriving on any of the three interfaces (i.e., Host
bus, hub interface or from the internal graphics device).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
| FWA-45A21F | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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