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參數(shù)資料
| 型號(hào)： | FX009ALS |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類(lèi)： | 音頻／視頻放大 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQCC24 |
| 封裝： | PLASTIC, LCC-24 |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | FX009ALS |
2
Pin Number
Function
FX009A
J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Serial Clock : This external clock pulse input is used to “clock in” the Control Data.
See Figure 4, Data Load Timing. This input has an internal 1M
pullup resistor.
Load/Latch : Governs the loading and execution of the control data. During serial
data loading this input should be kept at a logical '0' to ensure that data rippling past
the latches has no effect. When all 8 bits have been loaded, this input should be
strobed '0'
'1' '0' to latch the new data in. Data is executed on the falling edge
of the strobe. If the Load/Latch input is used this pin should be left open circuit. This
input has an internal 1M
pullup resistor.
Load/Latch : The inverted Load/Latch input. This function governs the loading and
execution of the control data. During serial data loading this input should be kept at a
logical '1' to ensure that data rippling past the latches has no effect. When all 8 bits
have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in.
Data is executed on the rising edge of the strobe. If the Load/Latch input is used this
pin should be left open circuit. This input has an internal 1M
pulldown resistor.
Ch1 Input :
Ch2 Input :
Ch3 Input :
Ch4 Input :
V
BIAS :
The output of the on-chip bias circuitry, held at V
DD/2.
This pin should be
decoupled to V
SS as shown in Figure 2.
Ch5 Input :
Ch6 Input :
Ch7 Input :
Ch8 Input :
V
SS :
Negative supply rail (GND).
Ch8 Output :
Ch7 Output :
Ch6 Output :
Ch5 Output :
No internal connection. Do not use.
Ch4 Output :
Ch3 Output :
Ch2 Output :
Ch1 Output :
V
DD :
Positive supply rail. A single +5-volt power supply is required.
Control Data Input : Operation of the 8 amplifier channels (Ch1 – Ch8) is controlled
by the 8 bits of data entered serially at this pin . The data is entered (bit 7 to bit 0) on
the rising edge of the external Serial Clock. The data format is described in Tables 1,
2 and Figure 4. This input has an internal 1M
pullup resistor.
Analogue Outputs :
The individual "Gain Controlled" amplifier outputs.
Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps, Ch8
could be utilized as a volume control, ranging from -14dB to
+14dB in 2.0dB steps.
In the powersave mode the selected output is biased at V
DD/2.
Analogue Outputs
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'
Analogue Inputs :
These individual amplifier inputs are self-biasing, a.c. input
analogue signals must be capacitively coupled to these pins,
as shown in Figure 2.
In the powersave modes the inputs are biased at V
DD/2.
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'
Analogue Inputs :
FX009A
LG/LS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FX009ALG | AUDIO AMPLIFIER, PQFP24 |
| FX009J | SPECIALTY TELECOM CIRCUIT, CDIP24 |
| FX009LS | SPECIALTY TELECOM CIRCUIT, PQCC24 |
| FX009LG | AUDIO AMPLIFIER, PQFP24 |
| FX029J | 2 CHANNEL, AUDIO AMPLIFIER, CDIP16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FX009J | 制造商:CMLMICRO 制造商全稱(chēng):CML Microcircuits 功能描述:Digitally Controlled Amplifier Array |
| FX009LG | 制造商:CMLMICRO 制造商全稱(chēng):CML Microcircuits 功能描述:Digitally Controlled Amplifier Array |
| FX009LS | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
| FX-01-000 | 制造商:AEARO 功能描述:EARPLUG E.A.R BANDED FLEXICAP |
| FX011Z | 制造商:Texas Instruments 功能描述:Dual Synchronous Step-down PWM Controlle |
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