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參數(shù)資料
| 型號： | FX029D5 |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2 CHANNEL, AUDIO AMPLIFIER, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 470K |
| 代理商： | FX029D5 |
4
Control Data and Timing
The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to
Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed,
6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for
output settings (D0-D3). This format is illustrated below in Figure 4.
Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection
and output settings, respectively.
GAIN/ATTENUATION
LEVEL
INPUT
SELECT
CHANNEL
ADDRESS
OUTPUT
SETTINGS
D13
D12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Fig.4 Level-Controlling Data Word Format
D13 D12 D11 D10
D9
D8
Gain
Set (dB)
0
MUTE
00
01
-48
00
10
-46
00
11
-44
00
01
00
-42
00
01
-40
00
01
10
-38
00
01
11
-36
00
10
00
-34
00
10
01
-32
00
10
-30
00
10
11
-28
00
11
00
-26
00
11
01
-24
00
11
10
-22
00
11
-20
01
00
-18
01
00
01
-16
01
00
10
-14
01
00
11
-12
01
00
-10
01
-8
01
10
-6
01
11
-4
01
10
00
-2
01
10
01
0
Table 1 - Amplification/Attenuation Level
D13 D12 D11 D10
D9
D8
Gain
Set (dB)
01
10
01
0
01
10
2
01
10
11
4
01
11
00
6
01
11
01
8
01
11
10
01
11
12
10
00
14
10
00
01
16
10
00
10
18
10
00
11
20
10
01
00
22
10
01
24
10
01
10
26
10
01
11
28
10
00
30
10
01
32
10
34
10
11
36
10
11
00
38
10
11
01
40
10
11
10
42
10
11
44
11
00
46
11
00
01
48
11
00
10
48
11
00
11
48
D7
Stage
D6
D5
D4
Inputs
Selected
0
1
0
none
1
2
001
1
010
2
0
1
1 and 2
100
3
1
0
1
1 and 3
1
0
2 and 3
1
1, 2 and 3
Table 2 Stage and Input Selection
D3
D2
Output
D1
D0
Outputs
1B
1A & 2
0
high Z
0
high Z
0
1
enabled
0
1
enabled
10
V
SS
10
V
SS
11
V
BIAS
11
V
BIAS
Table 3 Stage Output Selection
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