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參數(shù)資料
| 型號： | FX029DW |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2 CHANNEL, AUDIO AMPLIFIER, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 470K |
| 代理商： | FX029DW |
1
PRODUCT INFORMATION
CML Semiconductor Products
FX029
Features
2 Digitally Controlled Amplifiers
Gain/Attenuation Range of ±48dB
+ Output Mute, in 2dB Steps
Gain/Attenuation Levels Set by
Serial Interface
Separate Fixed-Gain Uncommitted
Amplifier
5 Volt Low-Power Operation
Applications
Cellular and PMR
Communications Systems
Automatic and Manual Test
Equipment
Remote Gain Adjustments
Telephone Audio Settings
Medical Equipment
Audio and Data Gain Setting
Applications
Brief Description
The FX029 single-chip Dual Digitally Controlled
Amplifier Array can replace manual audio-level
controls in most electronic applications including radio
and line communications systems.
The FX029 comprises two digitally controlled gain
and attenuation stages, with each stage having 48
distinct gain steps (range; between -48dB and +48dB
in 2dB steps) plus a MUTE state.
Both gain stages have selectable inputs. This switching
allows for selection of three different input signals
to stage 1 and two to stage 2.
Dual Digitally Controlled
Amplifier Array
Publication D/029/4 November 2003
Provisional Issue
FX029
Fig.1 Functional Block Diagram
Stage 1 also provides output switching.
In addition to the two digitally controlled gain stages,
there is a general purpose, uncommitted inverting
amplifier; the gain of this particular amplifier is
component controlled externally using negative
feedback.
Control of each gain stage section is accomplished
through the serial interface. All switching is
accomplished using controlled rise and fall times,
thereby ensuring no annoying transients (clicks or
pops).
The FX029 requires a single 5 volt supply and is
available in compact cerdip and small outline packages.
3
2
1B
1A
V
DD
V
BIAS
V
SS
Stage 1
Stage 1 Inputs
Stage 2 Inputs
Stage 3 Input
OUTPUTS
Control 1
Gain
V
BIAS
V
BIAS
V
SS
V
SS
Gain
SERIAL CLOCK
SERIAL DATA
Control 2
V
BIAS
6
Stage 2
-
+
IN 2A
IN 1A
IN 2B
IN 1B
IN 3
IN 1C
(UNCOMMITTED)
Stage 3
SERIAL
INTERFACE
STAGE 1
CONTROL
REGISTER
STAGE 2
CONTROL
REGISTER
LOAD/LATCH
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