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參數(shù)資料
| 型號： | G12290EJ2V0AN00 |
| 英文描述： | uPC1663 DC to VHF Wideband Differential Input and Output Amplifier IC |
| 中文描述： | uPC1663直流高頻寬帶差分輸入和輸出功放IC |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 165K |
| 代理商： | G12290EJ2V0AN00 |
8
Figure 2. Response to Sine Wave Input
IN
1
V
CC–
V
CC+
IN
2
OUT
1
OUT
2
2.2 Determination of Gain
Given r
e1
and r
e2
as the resistance values corresponding to the input differential transistors Q
1
and Q
2
, the gain
can be approximated via the following equations.
Gain A
VD1
for IN
1
and OUT
1
R
14
A
VD1
=
...........................(1)
r
e1
+ R
3
+ R
5
Gain A
VD2
for IN
2
and OUT
2
R
15
A
VD2
=
...........................(2)
r
e2
+ R
4
+ R
6
Consequently, assuming that
'
V
DIF
= V
IN1
e
V
IN2
as the differential voltage between IN
1
and IN
2
, the output
voltage can be calculated as follows.
|
'
V
DIF
|
|
'
OUT
1
| =
2
|
'
V
DIF
|
|
'
OUT
2
| =
2
x
A
VD1
........................(3)
x
A
VD2
........................(4)
Since A
VD1
= A
VD2
, we can add equations (3) and (4) to obtain the following.
|
'
OUT
1
| + |
'
OUT
2
|
A
VD1
=
...................(5)
|
'
V
DIF
|
In equations (3), (4), and (5), A
VD1
(A
VD2
) represents the differential output gain corresponding to the differential
input voltage. Therefore, the differential voltage gain and A
VD1
/2 (A
VD2
/2) are defined as single-end voltage gain
since it represents only one-sided output corresponding to the differential input voltage.
2.3 Gain Adjustments
The gain values shown in equations (1) and (2) in section 2.2 above are determined according to the resistance
applied to the emitter side of input differential transistors Q
1
and Q
2
.
Accordingly, in the equivalent circuit shown in Figure 1, a short between gain select pins G
1A
and G
1B
or insertion
of an adjusting resistor can be used to adjust the gain in steps.
Setting a short between G
1A
and G
1B
sets maximum gain, with a typical value of 320 times the differential gain.
Setting an open connection between G
1A
and G
1B
sets minimum gain, with a typical value of 10 times the differential
gain. The electrical characteristics for the two gain select pin conditions, when Gain 1 is the maximum gain and Gain
2 is the minimum gain, are shown in Table 3.
If a gain adjusting resistor is inserted between G
1A
and G
1B
(as shown in Figure 4), any desired gain level can be
obtained. Depending on the application circuit, if the Rs value is changed, the input voltage amplitude appears like it
fluctuates due to changes in the interstage impedance, but the gain of the IC itself does not vary.
.
.
.
.
Remark
For purposes of
simplification, the bypass
capacitor and gain select
pin have been omitted in
some figures, such as
Figure 2.
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