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參數(shù)資料
| 型號(hào)： | G2996P1UF |
| 廠商： | Global Mixed-mode Technology Inc. |
| 英文描述： | DDR I/II Termination Regulator |
| 中文描述： | 的DDR I / II型終端調(diào)節(jié)器 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 289K |
| 代理商： | G2996P1UF |
Ver: 2.3
May 16, 2006
TEL: 886-3-5788833
http://www.gmt.com.tw
10
G2996
Global Mixed-mode Technology Inc.
Typical Application Circuits
There are several application circuits shown in Figure
2 through 8 to illustrate some of the possible configu-
rations of the G2996. Figure 2~4 are the SSTL-2 ap-
plications. For the majority of applications that imple-
ment the SSTL-2 termination scheme, it is recom-
mended to connect all the input rails to 2.5V rail, as
seen in Figure 2. This provides an optimal trade-off
between power dissipation and component count.
In Figure 3, the power rails are split. The power rail of
the output stage (PVIN) can be as low as 1.8V, the
power rail of the analog circuit (AVIN) is operated
above 2V. The lower output stage power rail can lower
the internal power dissipation when sourcing from the
device and improve the efficiency, but the disadvan-
tage is the maximum continuous current sourcing from
VTT is reduced. This configuration is applied when the
power dissipation and efficiency are concerned.
In Figure 4, the power rail of the output stage (PVIN) is
connected to 3.3V to increase the maximum continu-
ous current sourcing from VTT. AVIN should be always
equal to or larger than PVIN. This configuration can
increase the source capability of this device, but the
power dissipation increases at the same time. It
should be more careful to prevent the junction tem-
perature from exceeding the maximum rating. Be-
cause of this risk, it is not recommended to supply the
output stage power rail (PVIN) with a voltage higher
than a nominal 3.3V rail.
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT=1.25V
V
REF=1.25V
V
DDQ=2.5V
V
DD=2.5V
SD
C
IN
Figure 2. Recommended SSTL-2 Implementation
C
OUT
C
REF
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT=1.25V
V
REF=1.25V
V
DDQ=2.5V
V
DD=2.5V
SD
C
IN
Figure 2. Recommended SSTL-2 Implementation
C
OUT
C
REF
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT=1.25V
V
REF=1.25V
V
DDQ=2.5V
AV
IN=3.3V or 5V
SD
C
IN
Figure 4. SSTL-2 Implementation with higher voltage rails
C
OUT
C
REF
PV
IN=3.3V
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT=1.25V
V
REF=1.25V
V
DDQ=2.5V
AV
IN=3.3V or 5V
SD
C
IN
Figure 4. SSTL-2 Implementation with higher voltage rails
C
OUT
C
REF
PV
IN=3.3V
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT=1.25V
V
REF=1.25V
V
DDQ=2.5V
AV
IN=1.8V or 5.5V
SD
C
IN
Figure 3. Lower Power Dissipation SSTL-2 Implementation
C
OUT
C
REF
PV
IN=1.8V
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT=1.25V
V
REF=1.25V
V
DDQ=2.5V
AV
IN=1.8V or 5.5V
SD
C
IN
Figure 3. Lower Power Dissipation SSTL-2 Implementation
C
OUT
C
REF
PV
IN=1.8V
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