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參數(shù)資料
| 型號： | G569C |
| 廠商： | Global Mixed-mode Technology Inc. |
| 英文描述： | CD-RW Laser Diode Current Driver |
| 中文描述： | CD - RW激光二極管電流驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 185K |
| 代理商： | G569C |
Ver: 1.0
Oct 02, 2000
TEL: 886-3-5788833
http://www.gmt.com.tw
5
G569C
Global Mixed-mode Technology Inc.
When VCDR = 0V, VCAGS = 5V, VRECORD = 0V
ICAGAIN = 1.2 x VCAGAIN / R108 + (VS2V9 - VCAGAIN) / R195,
When VCDR = 0V, VCAGS = 5V, VRECORD = 5V
ICAGAIN = 1.2 x VCAGAIN / R108
When VCDR = 0V, VCAGS = 0V, VRECORD = 0V
ICAGAIN = (VS2V9 - VCAGAIN) / R195,
When VCDR = 0V, VCAGS = 0V, VRECORD = 5V
ICAGAIN = 0 mA,
Where ICAGAIN is in mA; all voltages are in volt, and all
resistance are in K
Ω.
FSA Block
The FSOF/FSON control the integration of the
photodiode current, IFSA, on the capacitors connected
on pin FSCLR to obtain a voltage. The voltage on
FSCLR pin is connected to two sample-and-hold
circuit. The voltages sampled by the control voltage on
FSWS and FSRS pins are output on FSW and FSR
pins, respectively. Namely,
When VFSWS = 5V, VFSW = VFSCLR,
When VFSWS = 0V, VFSW = the previously sampled
value;
When VFSRS = 5V, VFSR = VFSCLR,
When VFSRS = 0V, VFSR = the previously sampled
value.
The charging of FSCLR node is controlled by signals
VFSOF and VFSON.
When VFSOF = 0V, the FSCLR pin is charged by IFSA.
When VFSOF = 5V, the FSCLR pin is not charged by IFSA.
The FSCLR, RDGAIN1, RDGAIN2, and RDGAIN3
pins are driven by an open-drain buffer, i.e., the
voltages on these pins are either 0V or Hi-Z. The
capacitance values of the three capacitors connecting
to the FSCLR may need to be changed if loader other
than CDL4800 is used.
When VFSCLR = 0V, the charges on the capacitors are
discharged to 0V.
When VFSCLR = Hi-Z, the charging of FSCLR node is
allowed.
When VRDGAIN1 = 0V, the VFSCLR is given by:
VFSCLR = IFSA x R187.
When VRDGAIN1 = Hi-Z, the charging of FSCLR node is
allowed.
When VRDGAIN2 = 0V, the capacitor C123 is in parallel
with C116.
When VRDGAIN2 = Hi-Z, the capacitor C123 has no effect.
When VRDGAIN3 = 0V, the capacitor C117 is in parallel
with C116.
When VRDGAIN3 = Hi-Z, the capacitor C117 has no effect.
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