參數(shù)資料
型號: G671L463T76U
廠商: Global Mixed-mode Technology Inc.
元件分類: 復位半導體
英文描述: Microprocessor Reset IC
中文描述: 微處理器復位IC
文件頁數(shù): 13/13頁
文件大?。?/td> 193K
代理商: G671L463T76U
Ver: 1.5
Dec 03, 2005
TEL: 886-3-5788833
http://www.gmt.com.tw
9
G670/G671
Global Mixed-mode Technology Inc.
Pin Description
NAME
FUNCTION
GND
Ground
(G671L/G670L)
RESET
Output remains low while VCC is below the reset threshold, and for at most 2ms after VCC rises
above the reset threshold.
RESET
(G670H)
RESET Output remains high while VCC is below the reset threshold, and for at most 2ms after VCC rises
above the reset threshold.
VCC
Supply Voltage (+5V, +3.3V, +3.0V)
Detailed Description
A microprocessor’s (P’s) reset input starts the P in a
known state. The G671L/G670L/G670H assert reset to
prevent
code-execution
errors
during
power-up,
power-down, or brownout conditions. They assert a
reset signal whenever the VCC supply voltage declines
below a preset threshold, keeping it asserted for at
most 2ms after VCC has risen above the reset thresh-
old. The G671L uses an open-drain output, and the
G670L/G670H have a push-pull output stage. Connect
a pull-up resistor on the G671L’s RESET output to any
supply between 0 and 5.5V.
Figure 1. Maximum Transient Duration Without
Causing a Reset Pulse vs. Reset Com-
parator Overdrive
Figure 2. RESET Valid to VCC = Ground Circuit
Applications Information
Negative-Going VCC Transients
In addition to issuing a reset to the P during power-up,
power-down, and brownout conditions, the G671L/
G670H/G670L are relatively immune to short- duration
negative-going VCC transients (glitches).
Figure 1 shows typical transient duration vs. reset
comparator overdrive, for which the G671L/G670H/
G670L do not generate a reset pulse. The graph was
generated using a negative-going pulse applied to VCC,
starting 0.5V above the actual reset threshold and
ending below it by the magnitude indicated (reset
comparator overdrive). The graph indicates the maxi-
mum pulse width a negative-going VCC transient can
have without causing a reset pulse. As the magnitude
of the transient increases (goes farther below the reset
threshold), the maximum allowable pulse width de-
creases. Typically, for the G67_ _463 and G67_ _438,
a VCC transient that goes 100mV below the reset
threshold and lasts 7s or less will not cause a reset
pulse. A 0.1F bypass capacitor mounted as close as
possible to the VCC pin provides additional transient
immunity.
Ensuring a Valid Reset Output Down to VCC = 0
When VCC falls below 1V, the G670 RESET output
no longer sinks current—it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
nected to RESET can drift to undetermined voltages.
This presents no problem in most applications since
most P and other circuitry is inoperative with VCC
below 1V. However, in applications where RESET
must be valid down to 0V, adding a pull-down resistor
to RESET causes any stray leakage currents to flow
to ground, holding RESET low (Figure 2). R1’s value
is not critical; 100k
Ω is large enough not to load
RESET and small enough to pull RESET to ground.
A 100k
Ω pull-up resistor to VCC is also recommended
for the G671L if RESET is required to remain valid
for VCC < 1V.
0
100
200
300
400
500
600
1
10
100
1000
Res et Com parator Overdrive, V
TH - V CC (m V )
M
a
x
im
u
m
T
rans
ient
D
u
ra
ti
on
(u
s
)
G67_ _ 308/293/263
G67_ _ 463/438/400
V
CC
RESET
GND
G670
R1
100k
V
CC
RESET
GND
G670
R1
100k
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