Specifications GAL16V8 15 fmax with Internal Feedback 1/(t
參數(shù)資料
型號: GAL16V8D-15LJN
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 9/26頁
文件大?。?/td> 0K
描述: SPLD 62.5MHZ EECMOS 20 PLCC
產(chǎn)品變化通告: Product Discontinuation 07/Sept/2010
標準包裝: 460
可編程類型: EE PLD
宏單元數(shù): 8
輸入電壓: 4.75 V ~ 5.25 V
速度: 15ns
安裝類型: 表面貼裝
封裝/外殼: 20-LCC(J 形引線)
供應商設備封裝: 20-PLCC(9x9)
包裝: 托盤
其它名稱: Q6536526
Specifications GAL16V8
15
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
REGISTER
LOGIC
ARRAY
CLK
tsu + th
REGISTER
LOGIC
ARRAY
tco
tsu
CLK
Test Condition
R1
R2
CL
A
200Ω
390Ω
50pF
B
Active High
390Ω
50pF
Active Low
200Ω
390Ω
50pF
C
Active High
390Ω
5pF
Active Low
200Ω
390Ω
5pF
CLK
REGISTER
LOGIC
ARRAY
tcf
tpd
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R2
R1
GAL16V8D (except -3) Output Load Conditions (see figure
above)
fmax Descriptions
Switching Test Conditions
Input Pulse Levels
Table 2-0003/16V8
Input Rise
and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
See figure at right
3-state levels are measured 0.5V from
steady-state active level.
2 – 3ns 10% – 90%
1.5ns 10% – 90%
GAL16V8D-10
(and slower)
GAL16V8D-3/-5/-7
ALL
DEVICES
DISCONTINUED
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GAL16V8D15LP 制造商:Lattice Semiconductor Corporation 功能描述:
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