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參數(shù)資料
| 型號(hào)： | GAL18V10B-20LJ |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLD 10MACRO 5.0V 20NS 20PLCC |
| 標(biāo)準(zhǔn)包裝： | 46 |
| 系列： | GAL®18V10 |
| 可編程類型： | EE PLD |
| 最大延遲時(shí)間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 10 |
| 工作溫度： | 0°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
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Specifications GAL18V10
3
GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL18V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
The GAL18V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registered outputs to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers
to a logic one on the rising edge of the next clock pulse after this
product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
The GAL18V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to ten prod-
uct terms (pins 14 and 15), and the other eight OLMCs have eight
product terms each. In addition to the product terms available for
logic, each OLMC has an additional product-term dedicated to out-
put enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
AR
SP
D
Q
CLK
4 T O 1
MU X
2 T O 1
MU X
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
ALL
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL18V10B-20LP | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 18 Input 10 Output 5V Low Power 20ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL18V10B-7LJ | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 18 INPUT 10 OUTPUT 5 V LOW POWER 7.5ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL18V10B-7LP | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 18 INPUT 10 OUTPUT 5 V LOW POWER 7.5ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL-1-OR | 制造商:Thomas & Betts 功能描述:1/2COND BX XPLPRF L STYL ORNG |
| GAL-2 | 制造商:Thomas & Betts 功能描述:Outlet Boxes Hazardous Locations |
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