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參數(shù)資料
| 型號(hào)： | GAL18V10B-20LP |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GAL 10OUT MACROCELL 7.5NS 20 |
| 產(chǎn)品變化通告： | Product Discontinuation 07/Sept/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 10 |
| 輸入電壓： | 4.75 V ~ 5.25 V |
| 速度： | 20ns |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 其它名稱： | Q6330552 |
Specifications GAL18V10
10
Electronic Signature
An electronic signature is provided in every GAL18V10 device. It
contains 64 bits of reprogrammable memory that can contain user-
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
Security Cell
A security cell is provided in every GAL18V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL18V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
Typical Input Current
1. 0
2. 0
3. 0
4. 0
5. 0
-6 0
0
-2 0
-4 0
0
Input V olt age ( V olt s)
Input
C
ur
re
nt
(
uA
)
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL18V10 device includes circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing test vectors
perform output register preload automatically.
Input Buffers
GAL18V10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The input and I/O pins also have built-in active pull-ups. As a result,
floating inputs will float to a TTL high (logic 1). However, Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins be connected to an adjacent active input, Vcc, or ground.
Doing so will tend to improve noise immunity and reduce Icc for the
device.
ALL
DEVICES
DISCONTINUED
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