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參數(shù)資料
| 型號： | GAL22V10D-25QJN |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 0K |
| 描述： | SPLD GAL 10 MACRO CELLS 38.5MHZ |
| 產(chǎn)品變化通告： | Product Discontinuation 07/Sept/2010 |
| 標準包裝： | 370 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 10 |
| 輸入電壓： | 4.75 V ~ 5.25 V |
| 速度： | 25ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 托盤 |
| 其它名稱： | Q6613932 |
Specifications GAL22V10
14
(Vref Typical = 3.2V)
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1μs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
Device Pin
Reset to Logic "0"
Vc c
CL K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Typical Input
Typical Output
Power-Up Reset
Input/Output Equivalent Schematics
ALL
DEVICES
DISCONTINUED
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參數(shù)描述 |
|---|---|
| GAL22V10D-25QP | 功能描述:SPLD - 簡單可編程邏輯器件 5V 22 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL22V10D25QPN | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10D-25QPN | 功能描述:SPLD - 簡單可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL22V10D-30LD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL22V10D-4LJ | 功能描述:SPLD - 簡單可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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