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參數(shù)資料
| 型號： | GIGAPHY_SD |
| 英文描述： | GigaPHY-LAB-KT Schematics and Layout? 1.13MB (PDF) |
| 中文描述： | GigaPHY -勞顧會的韓國電信原理圖和布局？ 1.13MB（PDF格式） |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 1158K |
| 代理商： | GIGAPHY_SD |
GigaPHY
(TM)
-SD Device
GDPHYSD_1B
Eval Board
Layout Considerations
The board has been designed in a simple, straightforward manner in which highest priority was given
to properly routing of high-speed signals. This four layer, controlled impedance PCB contains signal
layers on the top and bottom of the board with internal Power (Vdd=3.3V) and GND planes. Components
are mounted on both sides of the board so that passives may be placed as close as possible to their ideal
location regardless of which side of the board the part is placed. The PCB accommodates a special
socket for the AM79761 so placement of passives on the topside near the pins was not possible.
The 1Gb/s transmit and receive signals between the chipset and the connector were the first priority.
Since they form a differential PECL pair these traces were of minimal and equal length and, in this
example, have characteristic impedance of 50 ohm. The passive components should be packed as
closely as possible to minimize stub lengths and maximize signal quality. On the receiver inputs,
minimization of trace length between the AC Coupling Caps (C28/C29), the input pins (RX[+],RX[-]) and
the 182 ohm termination resistors are very important since the terminator resistors act as the virtual end
of the line. Stubs on these lines will cause degradation of signal quality into the receivers due to
reflections.
Diagonal corners were used so as to avoid the impedance mismatches found in right angle traces.
The same considerations as other high-speed signals apply here.
Transmit data jitter is generated through two main factors: Power Supply Noise and TBC jitter. Proper
layout of the REFCLK traces is essential to minimize REFCLK jitter into the part. Curved traces are used
to minimize reflections. Generous bypassing of the power supplies and separate isolation and decoupling
for each sensitive supply type is one easy method to eliminate much of this noise.
In general, common layout/placement techniques developed for lower speed PCBs apply here and
should lead to first-pass success.
Last Updated 11/04/97
1997 Advanced Micro Devices
Trademark Information
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| GIGASETA420ATRIO | 制造商:Siemens 功能描述:Gigaset A420A TRIO (FRENCH) |
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