參數(shù)資料
型號: GL841
英文描述: GL841 USB 2.0 2-in-1 Scanner Controller
中文描述: GL841的USB 2.0 2合1掃描儀控制器
文件頁數(shù): 10/50頁
文件大?。?/td> 1688K
代理商: GL841
GL841 USB 2.0 2-in-1 Scanner Controller
MT_PH0=I02
Uni-polar(2003) : MT_PH3=PHASE A
MT_PH2=PHASE B
MT_PH1=PHASE /A
MT_PH0=PHASE /B
MOTORTGO(GPIO13)
O
Output motor trigger for ADF scanning or GPIO13.
HOME
I
Sense carriage home position
CCD/CIS Control Signals
CCD_CK1X
O
CCD Shift register clock1 or CIS clock output
CCD_CK2X
O
CCD Shift register clock2 or CIS clock output
CCD_CPX
O
CCD Clamp gate clock or CIS clock output
CCD_RSX
O
CCD Reset gate clock or CIS clock output
CCD_TGX
O
CCD Transfer gate clock for R channel or CIS Line start pulse
CCD_TGG
O
CCD Transfer gate clock for G channel
CCD_TGB
O
CCD Transfer gate clock for B channel
CCD_CK3X
O
CCD Shift register clock3
CCD_CK4X
O
CCD Shift register clock4
LAMP_SW
O
Flatbed lamp power control or CIS Red LED array control
XPA_SW
O
Transparency lamp power control or CIS Green LED array control
LED_B
O
CIS Blue LED array control
FRONT-END
OP0~7
I
AFE digital data input.
SEN/SLOAD
O
Serial interface load pulse.
SCLK
O
Serial interface clock output.
SDI
O
Serial data output.
SDO
I
Serial data input.
BSMP/CDSCLK1
O
Wolfson type : Video sample synchronization pulse.
Analog Device : CDS Reference level sampling clock.
VSMP/CDSCLK2
O
Wolfson type : Video sample synchronization pulse.
Analog Device : CDS Data level sampling clock.
MCLK/ADCCLK
O
Wolfson type : Master clock.
Analog Device : A/D Converter sampling clock.
DRAM
DBUS0~15
B
DRAM data bus
ABUS0~9
O
DRAM address bus
RASX
O
DRAM RAS signal of first memory chip
CASX
O
DRAM CAS signal of first memory chip
NOEX
O
DRAM OE(output enable) signal of first memory chip
NWEX
O
DRAM WE signal of first memory chip
RASY
O
DRAM RAS signal of second memory chip
CASY
O
DRAM CAS signal of second memory chip
NOEY
O
DRAM OE(output enable) signal of second memory chip
NWEY
O
DRAM WE signal of second memory chip
Miscellaneous
Version 1.7
10
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