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參數(shù)資料
| 型號： | GM5125-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | GM5125-H |
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***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
14
C5115-DAT-01H
Vdd
GND
Oscillator
Internal
Oscillator
Reset State Logic
ROM_ADDR13
XTAL
TCLK
14 to 24 MHz
Vdd
OSC_OUT
TCLK Distribution
Internal Pull Down
Resistor
~ 60 K
Disable
gm5115/25
152
151
10
External Oscillator Enable
10 K
Vdd
Figure 7.
Using an External Single-ended Clock Oscillator
Frequency
Jitter Tolerance
Rise Time (10% to 90%)
Maximum Duty Cycle
14 to 24 MHz
250 ps
5 ns
40-60
Table 13.
TCLK Specification
4.1.3 Clock Synthesis
The gm5115/25 synthesis all additional clocks internally as illustrated in Figure 8 below. The
synthesized clocks are as follows:
1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is
derived from the TCLK/XTAL pad input.
2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference.
3. DVI Input Clock (DVI_CLK) synthesized by DVI receiver PLL using RC+/RC- pair as the
reference.
4. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input HSYNC
as the reference. The SDDS internal digital logic is driven by RCLK.
5. Display Clock (DCLK) synthesized by Destination DDS (DDDS) PLL using IP_CLK as the
reference. The DDDS internal digital logic is driven by RCLK.
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