參數(shù)資料
型號(hào): GMS37004T
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4-BIT SINGLE CHIP MICROCOMPUTERS
中文描述: 4-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù): 43/109頁
文件大小: 813K
代理商: GMS37004T
4-10
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of f
OSC
/6 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 6
2
13
/f
OSC
(108.026ms at f
OSC
=455KHz.)
8
6
2
13
/f
OSC
(108.026ms at f
OSC
= 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted.
f
OSC
/6 or f
OSC
/48
CPU reset
Reset
by instruction
Power-On Reset
Low VDD Detection
Binary counter(14 steps)
RESET (edge-trigger)
Fig. 4-7 Block Diagram of Watch-dog Timer
Chapter 4. FUNCTIONAL DESCRIPTION
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