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參數(shù)資料
| 型號(hào)： | GP1R |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Dual Mode CDMA/AMPS Baseband Interface |
| 中文描述： | 雙模式CDMA / AMPS二元基帶接口 |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大?。?/td> | 139K |
| 代理商： | GP1R |
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5
PLUTO
Parameter
Value
Units
Conditions
Min
Typ
Max
t1
TXCLOCK PERIOD (CDMA TX)
203.2
ns
CDMA TX Figure 3
t2
TXCLOCK HIGH TIME (CDMA TX)
101.6
ns
CDMA TX Figure 3
t3
TXCLOCK LOW TIME (CDMA TX)
101.6
ns
CDMA TX Figure 3
t4
TXCLOCK PHASE Delay (CDMA TX)
1.2
ns
CDMA TX Figure 3, FM TX Figure 4
t5
TXCLOCK RISE TIME (CDMA TX)
12
ns
CDMA TX Figure 3, FM TX Figure 4
t6
TXCLOCK FALL TIME (CDMA TX)
12
ns
CDMA TX Figure 3, FM TX Figure 4
t7
TXD-TXCLOCK SETUP TIME
20
ns
CDMA TX Figure 3, FM TX Figure 4
t8
TXCLOCK-TXD HOLD TIME
3
ns
CDMA TX Figure 3, FM TX Figure 4
t11
TXCLOCK PERIOD (FM TX)
2.78
s
FM TX Figure 4
t12
TXCLOCK HIGH TIME (FM TX)
1.39
s
FM TX Figure 4
t13
TXCLOCK LOW TIME (FM TX)
1.39
s
FM TX Figure 4
t14
CHIPx8 PERIOD
101.6
ns
Figure 5
t15
CHIPx8 HIGH TIME
50.8
ns
Figure 5
t16
CHIPx8LOW TIME
50.8
152.4
ns
Figure 5
t17
CHIPx8 RISE TIME
3
12
ns
Figure 5
t18
CHIPx8 FALL TIME
3
12
ns
Figure 5
t19
RXD Hold Time After CHIPx8
↓
10
ns
Figure 5
t20
RXD DELAY After CHIPx8
↓
20
ns
Figure 5
t21
FMCLK PERIOD
2.78
s
FM RX Figure 6
t22
FMCLK HIGH TIME
1.39
s
FM RX Figure 6
t23
FMCLK LOW TIME
1.39
s
FM RX Figure 6
t24
FMCLK RISE TIME
12
ns
FM RX Figure 6
t25
FMCLK FALL TIME
12
ns
FM RX Figure 6
t26
RXFMSTB HIGH TIME
1
s
FM RX Figure 6
t27
RXFMSTB -FMCLK
↓ SETUP TIME
50
ns
FM RX Figure 6
t28
FMCLK
↓ RXFMSTB HOLD TIME
50
ns
FM RX Figure 6
t29
FMCLK
↓ OUTPUT DATA DELAY
50
ns
FM RX Figure 6
t30
ADCENA HIGH _ CONVERSION
40
s
General purpose ADC Figure 7
t31
ADCENA HIGH TIME
100
ns
General purpose ADC Figure 7
t32
ADCENA LOW TIME
100
ns
General purpose ADC Figure 7
t33
ADCCLK PERIOD
2.44
s
General purpose ADC Figure 7
t34
ADCCLK HIGH TIME
0.81
s
General purpose ADC Figure 7
t35
ADCCLK LOW TIME
1.62
s
General purpose ADC Figure 7
t36
ADCCLK RISE TIME
12
ns
General purpose ADC Figure 7
t37
ADCCLK FALL TIME
12
ns
General purpose ADC Figure 7
t38
ADCDATA VALID BEFORE ADCCLK
↑
1
s
General purpose ADC Figure 7
t39
ADC DATA HOLD TIME
5
ns
General purpose ADC Figure 7
t40
SCLK-SDATA setup time
20
ns
Serial Interface Figure 8
t41
SCLK-SDATA hold time
20
ns
Serial Interface Figure 8
t42
SCLK pulse width
50
ns
Serial Interface Figure 8
t43
SLATCH-SCLK setup time
20
ns
Serial Interfsce Figure 8
t44
SLATCH pulse width
50
ns
Serial Interface Figure 8
t45
SCLK period
100
ns
Serial Interface Figure 8
TIMING INFORMATION
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