參數(shù)資料
型號: GP2015
廠商: Mitel Networks Corporation
英文描述: Aluminum Electrolytic Radial Leaded Low Profile Wide Temp Capacitor; Capacitance: 22uF; Voltage: 25V; Case Size: 5x9 mm; Packaging: Bulk
中文描述: GPS接收機射頻前端
文件頁數(shù): 21/24頁
文件大?。?/td> 154K
代理商: GP2015
GP2015
6
PIN DESCRIPTIONS
All VEE and VCC/VDD pins must be connected to ensure correct operation
Pin No.
Signal Name
Input/Output
Description
1
IFOutput
Output
IF Test output.
Connected to output of Stage 3 prior to the A to D converter.
A series 1k
resistor is incorporated for buffering purposes.
2
PLL Filter 1
Output
PLL Filter 1.
Connected to the bias network within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 2 (see below).
3
PLL Filter 2
Output
PLL Filter 2.
Connected to the varactor diodes within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 1 (see above).
4,6
VEE (OSC)
Input
Negative supply to the on-chip VCO. (See Note 1)
5VCC (OSC)
Input
Positive supply to the on-chip VCO.
7VEE (REG)
Input
Negative supply to the VCO regulator.
This must be connected to GND.
8
PRef
Input
Power-on Reset Reference input.
An on-chip comparator produces a logic HI when the PRef
input voltage exceeds +1.21V. (Nom) (See Page 3)
9
PReset
Output
Power-on Reset Output.
A TTL compatible output controlled by the Power-on reset
comparator (See above). This output remains active even
when the chip is powered down. (See pin 19 - PDn).
10
VEE (IO)
Input
Negative supply to the Digital Interface. (See Note 2)
11
CLK
Input
Sample Clock input from the correlator chip.
A TTL compatible input (which operates at 5.714MHz if used
with GP2021 correlator device) used to clock the MAG & SIGN
output latches, on the rising edge of the CLK signal.
12, 13
N/C
Not connected. (See Note 4)
14
MAG
Output
Magnitude bit data output.
A TTL compatible signal, representing the
magnitude of the
mixed down IF signal. Derived from the on-chip 2-bit A to D
converter, synchronised to the CLK input clock signal.
15
SIGN
Output
Sign bit data output.
A TTL compatible signal, representing the
polarity of the mixed
down IF signal. Derived from the on-chip 2-bit A to D converter,
synchronised to the CLK input clock signal.
16
OPClk-
Output
40MHz Clock output - inverse phase.
One side of a balanced differential output clock, with opposite
polarity to Pin 17 - OPClk+. Used to drive a master-clock signal
within the correlator chip.
17
OPClk+
Output
40MHz Clock output - true phase.
Other side of a balanced differential output clock set, with
opposite polarity to Pin 16 - OPClk-. Used to drive a master-
clock signal within the correlator chip.
相關(guān)PDF資料
PDF描述
GP2015 GPS Receiver RF Front End(用于全球定位系統(tǒng)(GPS)接收器的第二代RF前端)
GP2021 GPS 12 channel Correlator(用于全球定位系統(tǒng)(GPS)接收器的12通道的C/A代碼基帶相關(guān)器)
GP2021 GPS 12 channel Correlator Advance Information
GRM40Y5V105Z16 Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:21; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight
GRM42-6X5R475K10 50/100M SOT-23 CMOS RF LDO REGULATORS
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