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參數(shù)資料
| 型號(hào)： | GRM42-6X5R475K10 |
| 廠商： | Impala Linear Corporation |
| 英文描述： | 50/100M SOT-23 CMOS RF LDO REGULATORS |
| 中文描述： | 50/100M的SOT - 23 CMOS射頻LDO穩(wěn)壓器 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 424K |
| 代理商： | GRM42-6X5R475K10 |
50/100mA SOT-23 CMOS RF LDO Regulators
Impala Linear Corporation
8
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
The Effects of ESR (Equivalent Series Resistance)
The ESR of a capacitor is a measure of the resistance due
to the leads and the internal connections of the component.
Typically measured in m
(milli-ohms) it can increase to
ohms in some cases.
Wherever there is a combination of resistance and current,
voltages will be present. The control functions of LDOs use
two voltages in order to maintain the output precisely; VOUT
and VREF.
With reference to the block diagram in figure 2, VOUT is fed
back to the error amplifier and is used as the supply volt-
age for the internal components of the 7080/81. So any
change in VOUT will cause the error amplifier to try to com-
pensate to maintain VOUT at the set level and noise on
VOUT will be reflected into the supply of each internal cir-
cuit. The reference voltage, VREF, is influenced by the
CNOISE pin. Noise into this pin will add to the reference volt-
age and be fed through the circuit. These factors will not
cause a problem if some simple steps are taken. Figure 5
shows where these added ESR resistances are present in
the typical LDO circuit.
With this in mind low ESR components will offer better per-
formance as LDOs may be exposed to large transients of
output voltage, and current flows through the capacitors in
order to filter these transient swings. ESR is less of a prob-
lem with CIN as the voltage fluctuations at the input will be
filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of
several currents can develop detectable voltage ripple and
will be amplified by the LDO. Particularly the accumulation
of current flows in the ground plane can develop significant
voltages unless care is taken.
With a degree of care, the ILC7080/81 will yield outstanding
performance.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full
advantage of any high performance LDO regulator requires
paying careful attention to grounding and printed circuit
board (PCB) layout.
Figure 7 shows the effects of poor grounding and PCB lay-
out caused by the ESR and PCB resistances and the accu-
mulation of current flows.
Note particularly that during high output load current, the
LDO regulator’s ground pin and the ground return for COUT
and CNOISE are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current
loop between COUT, CNOISE and the LDO regulator’s ground
pin will degrade performance of the LDO.
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground cur-
rent and noise bypass current return of the LDO regulator.
Note that the key difference here is that COUT and CNOISE
are directly connected to the LDO regulator’s ground pin.
The LDO is then separately connected to the main ground
plane and returned to a single point system ground.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
V
OUT
V
IN
ILC7080
ILC7081
C
OUT
C
NOISE
SOT23-5
ON
OFF
R*
R
C
I
OUT
I
C
4
5
12
3
R*
C
IN
RF LDOTM
Regulator
ILC7080
ILC7081
V
IN
C
OUT
C
NOISE
SOT23-5
ESR
R
PCB
I
2
V
OUT
I
OUT
R
PCB
ESR
I
1
R
PCB
R
PCB
4
5
12
3
V
IN
R
PCB
ON
OFF
5
4
3
2
1
LOAD
Figure 5: ESR in COUT and CNOISE
Figure 6: Inherent PCB resistance
Figure 7: Effects of poor circuit layout
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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