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GENNUM CORPORATION
522 - 33 - 00
5
G
13
TRS_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-insertion of the
TRS into the data stream. When TRS_INS is high, the device re-
inserts TRS into the incoming data stream based on the internal
calculation. The original TRS packets are set to the blanking levels.
If the flywheel is enabled, TRS calculated by the flywheel is used for
insertion. When TRS_INS is low, the device will not re-insert TRS
even if errors in TRS signals are detected.
15
LN_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-insertion of the
line number into the data stream. When LN_INS is high, the device
re-inserts the line number into the incoming data stream based on
the internal calculation. The original line number packets are set to
the blanking levels. If the flywheel is enabled, the line number
calculated by the flywheel is used for insertion. When LN_INS is low,
the device will not re-insert the line number.
16
CRC_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-insertion of the
CRC into the data stream. When CRC_INS is high, the device is
enabled to re-insert line CRCs based on the internal calculation.
When CRC_INS is low, the device will not re-insert the CRCs.
17
FAST_LOCK
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
Used to control the flywheel synchronization
when a switch line occurs. When a low to high transition occurs on
the FAST_LOCK signal, the internal flywheel will immediately re-
synchronize to the next valid EAV or SAV TRS in the incoming data
stream. See Fig. 5 for timing information.
18
RESET
Non-
synchronous
Input
Control Signal Input.
Used to reset the system state registers to their
default 720p parameters. When RESET is high, the fly wheel, TRS
Detection, and ANC Detection operate normally. When RESET is
low, the flywheel, TRS Detection, and ANC Detection are reset to the
720p parameters after a rising edge on PCLK_IN. The read and
write counters are not affected.
21
H
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
This signal indicates the Horizontal blanking
period of the video signal. Refer to Fig. 2 for timing information of H
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively.
22
V
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
This signal indicates the Vertical blanking
period of the video signal. Refer to Fig. 2 for timing information of V
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively.
23
F
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
This signal indicates the ODD/EVEN field of
the video signal. Refer to Fig. 2 for timing information of F relative to
DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA
respectively. When locked and the input signal is of a progressive
scan nature, F stays low at all times.
26
ANC_DATA_Y
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
This signal indicates the position of the
embedded ANC data in the outgoing LUMA (DATA_OUT [19:10])
data stream. ANC_DATA_Y goes high for the entire time that an
ANC_DATA packet is present in the LUMA (DATA_OUT[19:10]) data
stream whether it be in the active video area or the ANC area. Refer
to Fig. 17 for timing of ANC_DATA_Y relative to LUMA
(DATA_OUT[19:10]). During detection of ANC data, any errors in the
data count (DC) packet will consequently cause errors in the
duration of the flags. Bit errors in an ANC header will prevent the
packet from being detected.
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION