參數(shù)資料
型號(hào): GS72108TP-12I
廠商: Electronic Theatre Controls, Inc.
英文描述: 256K x 8 2Mb Asynchronous SRAM
中文描述: 256K × 8的2Mb異步SRAM
文件頁(yè)數(shù): 6/12頁(yè)
文件大小: 364K
代理商: GS72108TP-12I
Rev: 1.08 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6/12
1999, Giga Semiconductor, Inc.
GS72108TP/J
AC Characteristics
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V
IL
, WE = V
IH
Read Cycle
Parameter
Symbol
-8
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
8
10
12
15
ns
Address access time
t
AA
8
10
12
15
ns
Chip enable access time (CE)
t
AC
8
10
12
15
ns
Output enable to output valid (OE)
t
OE
3.5
4
5
6
ns
Output hold from address change
t
OH
3
3
3
3
ns
Chip enable to output in low Z (CE)
t
LZ
*
3
3
3
3
ns
Output enable to output in low Z (OE)
t
OLZ
*
0
0
0
0
ns
Chip disable to output in High Z (CE)
t
HZ
*
4
5
6
7
ns
Output disable to output in High Z (OE)
t
OHZ
*
3.5
4
5
6
ns
t
AA
t
OH
t
RC
Address
Data Out
Previous Data
Data valid
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