參數(shù)資料
    型號(hào): GS8161Z36BGT-250
    廠商: GSI TECHNOLOGY
    元件分類: DRAM
    英文描述: 18Mb Pipelined and Flow Through Synchronous NBT SRAM
    中文描述: 512K X 36 ZBT SRAM, 5.5 ns, PQFP100
    封裝: ROHS COMPLIANT, TQFP-100
    文件頁數(shù): 1/37頁
    文件大小: 618K
    代理商: GS8161Z36BGT-250
    GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
    18Mb Pipelined and Flow Through
    Synchronous NBT SRAM
    2.5 V or 3.3 V V
    DD
    2.5 V or 3.3 V I/O
    Commercial Temp
    Industrial Temp
    Preliminary
    Rev: 1.00 9/2004
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    1/37
    2004, GSI Technology
    Features
    User-configurable Pipeline and Flow Through mode
    NBT (No Bus Turn Around) functionality allows zero wait
    read-write-read bus utilization
    Fully pin-compatible with both pipelined and flow through
    NtRAM, NoBL and ZBT SRAMs
    IEEE 1149.1 JTAG-compatible Boundary Scan
    2.5 V or 3.3 V +10%/–10% core power supply
    LBO pin for Linear or Interleave Burst mode
    Pin-compatible with 2M, 4M, and 8M devices
    Byte write operation (9-bit Bytes)
    3 chip enable signals for easy depth expansion
    ZZ pin for automatic power-down
    JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
    packages
    Pb-Free 100-lead TQFP package available
    Functional Description
    The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
    is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
    like ZBT, NtRAM, NoBL or other pipelined read/double late
    write or flow through read/single late write SRAMs, allow
    utilization of all available bus bandwidth by eliminating the
    need to insert deselect cycles when the device is switched from
    read to write cycles.
    Because it is a synchronous device, address, data inputs, and
    read/ write control inputs are captured on the rising edge of the
    input clock. Burst order control (LBO) must be tied to a power
    rail for proper operation. Asynchronous inputs include the
    Sleep mode enable, ZZ and Output Enable. Output Enable can
    be used to override the synchronous control of the output
    drivers and turn the RAM's output drivers off at any time.
    Write cycles are internally self-timed and initiated by the rising
    edge of the clock input. This feature eliminates complex off-
    chip write pulse generation required by asynchronous SRAMs
    and simplifies input signal timing.
    The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
    may be configured by the user to operate in Pipeline or Flow
    Through mode. Operating as a pipelined synchronous device,
    in addition to the rising-edge-triggered registers that capture
    input signals, the device incorporates a rising-edge-triggered
    output register. For read cycles, pipelined SRAM output data is
    temporarily stored by the edge triggered output register during
    the access cycle and then released to the output drivers at the
    next rising edge of clock.
    The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
    is implemented with GSI's high performance CMOS
    technology and is available in JEDEC-standard 100-pin TQFP
    and 165-bump FP-BGA packages.
    Parameter Synopsis
    -250
    2.5
    4.0
    280
    330
    -200
    3.0
    5.0
    230
    270
    -150
    3.8
    6.7
    185
    210
    Unit
    ns
    ns
    mA
    mA
    Pipeline
    3-1-1-1
    t
    KQ
    (x18/x36)
    tCycle
    Curr
    (x18)
    Curr
    (x32/x36)
    t
    KQ
    tCycle
    Curr
    (x18)
    Curr
    (x32/x36)
    Flow Through
    2-1-1-1
    5.5
    5.5
    210
    240
    6.5
    6.5
    185
    205
    7.5
    7.5
    170
    190
    ns
    ns
    mA
    mA
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