參數(shù)資料
型號: GS816272CGC-30I
廠商: GSI TECHNOLOGY
英文描述: 256K x 72 18Mb S/DCD Sync Burst SRAMs
中文描述: 256 × 72 35.7的S /雙氰胺同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 5/31頁
文件大小: 678K
代理商: GS816272CGC-30I
GS816272CC-333/300/250/200/150
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 2/2005
5/31
2004, GSI Technology
Mode Pin Functions
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Power Down Control
ZZ
L or NC
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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