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    參數(shù)資料
    

    


    


    
型號(hào)：
GS8162Z36B-133I

    

    
廠商：
GSI TECHNOLOGY

    

    
元件分類：
DRAM

    

    
英文描述：
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
中文描述：
512K X 36 ZBT SRAM, 8.5 ns, PBGA119

    

    
封裝：
FBGA-119

    

    
文件頁(yè)數(shù)：
28/38頁(yè)

    

    
文件大?。?/td>
838K

    

    
代理商：
GS8162Z36B-133I


    

    

    

	
    
    
    

    
    
	
    Tex8adx6prsi hsseiiainaeNtRcmmne o NwDsg.
    GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    Rev:  2.21  11/2004
    28/38
     1999, GSI Technology
    Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. 
    Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output 
    drivers on the falling edge of TCK when the controller is in the Update-IR state.
    tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
    ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR 
    state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
    ated. 
    IDCODE
    The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and 
    places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction 
    loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
    SAMPLE-Z
    If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
    Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR 
    state.
    RFU
    These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
    JTAG TAP Instruction Set Summary
    Instruction
    Code
    Description
    Notes
    EXTEST
    000
    Places the Boundary Scan Register between TDI and TDO.
    1
    IDCODE
    001
    Preloads ID Register and places it between TDI and TDO.
    1, 2
    SAMPLE-Z
    010
    Captures I/O ring contents. Places the Boundary Scan Register between TDI and 
    TDO. 
    Forces all RAM output drivers to High-Z.
    Do not use this instruction;  Reserved for Future Use.
    Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
    Captures I/O ring contents. Places the Boundary Scan Register between TDI and 
    TDO. 
    1
    RFU
    011
    1
    SAMPLE/
    PRELOAD
    100
    1
    GSI
    101
    GSI private instruction.
    1
    RFU
    110
    Do not use this instruction;  Reserved for Future Use.
    Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
    Places Bypass Register between TDI and TDO.
    1
    BYPASS
    111
    1
    Notes:
    1.
    2.
    Instruction codes expressed in binary, MSB on left, LSB on right.
    Default instruction automatically loaded at power-up and in test-logic-reset state.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
GS8162Z36B-150
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8162Z36B-150I
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8162Z36B-166
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8162Z36B-166I
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8162Z36B-200
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
GS8162Z36BB-150
 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 119FBGA - Trays

    

    
GS8162Z36BD-150
 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays

    

    
GS8162Z36BD-150I
 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays

    

    
GS8162Z36BD-150IV
 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays

    

    
GS8162Z36BD-150V
 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays

    

    
    
    
    
	
    	
    
    
     
     
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