參數(shù)資料
型號(hào)： GS8162Z36B-150
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 512K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝： FBGA-119
文件頁(yè)數(shù)： 25/38頁(yè)
文件大小： 838K
代理商： GS8162Z36B-150
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.21 11/2004
25/38
1999, GSI Technology
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
相關(guān)PDF資料
PDF描述
GS8162Z36B-150I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z36B-166 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z36B-166I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z36B-200 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z36B-200I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8162Z36BB-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 119FBGA - Trays
GS8162Z36BD-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays
GS8162Z36BD-150I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays
GS8162Z36BD-150IV 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays
GS8162Z36BD-150V 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays
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