參數(shù)資料
型號(hào): GS840F36A
廠商: GSI TECHNOLOGY
英文描述: 4Mb(128K x 36Bit) Synchronous Burst SRAM(4M位(128K x 36位)同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
中文描述: 4Mb的(128K的x 36Bit)同步突發(fā)靜態(tài)存儲(chǔ)器(4分位(128K的× 36位)同步靜態(tài)隨機(jī)存儲(chǔ)器(帶2位脈沖地址計(jì)數(shù)器))
文件頁(yè)數(shù): 7/22頁(yè)
文件大?。?/td> 795K
代理商: GS840F36A
Rev: 1.04 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
7/22
1999, Giga Semiconductor, Inc.
.
Preliminary
GS840F18/32/36AT-7.5/8/8.5/10/12
Mode Pin Functions
Note:
There is a are pull-up devices on the LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Byte Write Truth Table
Notes:
1.
2.
3.
4.
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
A
, B
B
, B
C,
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
C
” and “
D
” are only available on the x32 and x36 versions.
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
H or NC
L
H or NC
L or NC
Output Register Control
FT
Power Down Control
ZZ
H
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte
A
H
L
L
H
H
H
2, 3
Write byte
B
H
L
H
L
H
H
2, 3
Write byte
C
H
L
H
H
L
H
2, 3, 4
Write byte
D
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
1st address
2nd address
3rd address
4th address
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