參數(shù)資料
型號(hào): GS841Z36AGT-180I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 4Mb Pipelined and Flow Through Synchronous NBT SRAMs
中文描述: 128K X 36 ZBT SRAM, 8 ns, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 20/30頁
文件大?。?/td> 495K
代理商: GS841Z36AGT-180I
GS841Z18/36AT-180/166/150/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 11/2004
20/30
2001, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
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