參數(shù)資料
型號: GS8640FZ18T-8IVT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 4M X 18 ZBT SRAM, 8 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 16/19頁
文件大?。?/td> 456K
代理商: GS8640FZ18T-8IVT
GS8640FZ18/36T-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00a 2/2009
6/19
2007, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function
W
BA
BB
BC
BD
Read
H
X
Write Byte “a”
L
H
Write Byte “b”
L
H
L
H
Write Byte “c”
L
H
L
H
Write Byte “d”
L
H
L
Write all Bytes
L
Write Abort/NOP
L
H
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