參數(shù)資料
型號: GS864418E-250I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
中文描述: 4M X 18 CACHE SRAM, 6.5 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數(shù): 6/32頁
文件大?。?/td> 811K
代理商: GS864418E-250I
Mode Pin Functions
Mode Name
Pin Name
State
L
H
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
Preliminary
GS864418/36E-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 6/2006
6/32
2003, GSI Technology
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
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