參數(shù)資料
型號(hào)： GS8662D11BGD-400
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 7/34頁(yè)
文件大?。?/td> 670K
代理商： GS8662D11BGD-400
Thermal Impedance
Package
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
165 BGA
4-layer
22.300
18.572
17.349
9.292
2.310
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
15/34
2011, GSI Technology
GS8662D20/38BD-550/500/450/400/350
GS8662D06/11BD-500/450/400/350
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
Input Reference Voltage
VREF
VDDQ /2 – 0.05
VDDQ /2 + 0.05
V
—
Input High Voltage
VIH1
VREF + 0.1
VDDQ + 0.3
V
1
Input Low Voltage
VIL1
–0.3
VREF – 0.1
V
1
Input High Voltage
VIH2
0.7 * VDDQ
VDDQ + 0.3
V
2,3
Input Low Voltage
VIL2
–0.3
0.3 * VDDQ
V
2,3
Notes:
1. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
3. Parameters apply to ZQ during JTAG boundary scan testing only.
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
Input Reference Voltage
VREF
VDDQ /2 – 0.08
VDDQ /2 + 0.08
V
—
Input High Voltage
VIH1
VREF + 0.2
VDDQ + 0.5
V
1,2,3
Input Low Voltage
VIL1
–0.5
VREF – 0.2
V
1,2,3
Input High Voltage
VIH2
VDDQ – 0.2
VDDQ + 0.5
V
4,5
Input Low Voltage
VIL2
–0.5
0.2
V
4,5
Notes:
1. VIH(MAX) and VIL(MIN) apply for pulse widths less than one-quarter of the cycle time.
2. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.
3. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
5. Parameters apply to ZQ during JTAG boundary scan testing only.
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