參數(shù)資料
型號(hào)： GS88118T-11.5
英文描述： x18 Fast Synchronous SRAM
中文描述： x18快速同步SRAM
文件頁(yè)數(shù)： 6/33頁(yè)
文件大?。?/td> 616K
代理商： GS88118T-11.5
Rev: 1.10 7/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
6/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
ByteSafe
Parity Functions
This SRAMincludes a write data parity check that checks the validity of data comng into the RAMon write cycles. In Flow Through mode, write
data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later. (See
Write Parity Error Output Timing Diagram
.) The Data Parity Mode (DP) pin must be tied high to set the RAMto check for even parity or low to
check for odd parity. Read data parity is not checked by the RAMas data. Validity is best established at the data’s destination. The Parity Error
Output is an open drain output and drives low to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
Write Parity Error Output Timing Diagram
BPR 1999.05.18
CK
D In A
D In B
D In C
D In D
D In E
tKQ
tLZ
DQ
QE
F
P
tKQ
tLZ
DQ
QE
D In A
D In B
D In C
D In D
D In E
Err A
Err A
Err C
Err C
tHZ
tKQX
tHZ
tKQX
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GS88118T-11I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM
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GS88118T-66I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM
GS88118T-80 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM
GS88118T-80I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM
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