參數(shù)資料
型號: GS881Z36BGT-200T
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 36 ZBT SRAM, 6.5 ns, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 20/39頁
文件大?。?/td> 1318K
代理商: GS881Z36BGT-200T
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
Rev: 1.06a 2/2008
27/39
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
Not
Recommended
for
New
Design
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