參數(shù)資料
型號(hào): GS88237BD-333
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 256K x 36 9Mb SCD/DCD Sync Burst SRAM
中文描述: 256K X 36 CACHE SRAM, 2 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 22/29頁(yè)
文件大?。?/td> 577K
代理商: GS88237BD-333
GS88237BB/D-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 3/2005
22/29
2002, GSI Technology
JTAG Port AC Test Conditions
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
110
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Parameter
Conditions
V
DD
– 0.2 V
0.2 V
1 V/ns
V
DDQ
/2
V
DDQ
/2
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
相關(guān)PDF資料
PDF描述
GS88237BD-333I 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-200 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-200I 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-250 256K x 36 9Mb SCD/DCD Sync Burst SRAM
GS88237BGB-250I 256K x 36 9Mb SCD/DCD Sync Burst SRAM
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