- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄173641 > GS88237CB-200IT (GSI TECHNOLOGY) 256K X 36 CACHE SRAM, 2.7 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號： | GS88237CB-200IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 36 CACHE SRAM, 2.7 ns, PBGA119 |
| 封裝： | FPBGA-119 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 596K |
| 代理商： | GS88237CB-200IT |
GS88237CB-333/300/250/200
256K x 36
9Mb SCD/DCD Sync Burst SRAM
333 MHz–200 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
119-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.01 7/2009
1/26
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
Features
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119-bump BGA packages
Ro-HS Compliant 119-bump BGA packages available
Functional Description
Applications
The GS88237CB is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
SCD and DCD Pipelined Reads
The GS88237CB is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88237CB operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333 -300 -250 -200 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.0
3.0
2.2
3.3
2.3
4.0
2.7
5.0
ns
3.3 V
Curr (x36)
TBD TBD TBD TBD mA
2.5 V
Curr (x36)
TBD TBD TBD TBD mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS882V37BGB-360I | 256K X 36 CACHE SRAM, 1.8 ns, PBGA119 |
| GS9012E/E6 | 500 mA, 20 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-226AA |
| GS9012G/E6 | 500 mA, 20 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-226AA |
| GSAA01B-Q03 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 6A, 120VDC, 30.5mm, PANEL MOUNT |
| GSAA03B-Q01 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 6A, 120VDC, 30.5mm, PANEL MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS88237CB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 2.5NS 119FPBGA - Trays |
| GS88237CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 9MBIT 256KX36 2.5NS 119FPBGA - Trays |
| GS88237CB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.3NS 119FPBGA - Trays |
| GS88237CB-300 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2.2NS 119FPBGA - Trays |
| GS88237CB-333 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 256KX36 2NS 119FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。