參數(shù)資料
型號(hào)： GS882Z36B-66
廠商： Electronic Theatre Controls, Inc.
英文描述： 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
中文描述： 8MB的流水線和流量，通過(guò)同步唑靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 7/34頁(yè)
文件大小： 802K
代理商： GS882Z36B-66
Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
7/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
Synchronous Truth Table
Operation
Type Address E
1
E
2
E
3
ZZ ADV W Bx G CKE CK
DQ
Notes
Deselect Cycle, Power Down
D
None
H
X
X
L
L
X
X
X
L
L-H
High-Z
Deselect Cycle, Power Down
D
None
X
X
H
L
L
X
X
X
L
L-H
High-Z
Deselect Cycle, Power Down
D
None
X
L
X
L
L
X
X
X
L
L-H
High-Z
Deselect Cycle, Continue
D
None
X
X
X
L
H
X
X
X
L
L-H
High-Z
1
Read Cycle, Begin Burst
R
External
L
H
L
L
L
H
X
L
L
L-H
Q
Read Cycle, Continue Burst
B
Next
X
X
X
L
H
X
X
L
L
L-H
Q
1,10
NOP/Read, Begin Burst
R
External
L
H
L
L
L
H
X
H
L
L-H
High-Z
2
Dummy Read, Continue Burst
B
Next
X
X
X
L
H
X
X
H
L
L-H
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L
H
L
L
L
L
L
X
L
L-H
D
3
Write Cycle, Continue Burst
B
Next
X
X
X
L
H
X
L
X
L
L-H
D
1,3,10
NOP/Write Abort, Begin Burst
W
None
L
H
L
L
L
L
H
X
L
L-H
High-Z
2,3
Write Abort, Continue Burst
B
Next
X
X
X
L
H
X
H
X
L
L-H
High-Z
1,2,3,10
Clock Edge Ignore, Stall
Current
X
X
X
L
X
X
X
X
H
L-H
-
4
Sleep Mode
None
X
X
X
H
X
X
X
X
X
X
High-Z
Notes:
1.
Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.
G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
2.
3.
4.
5.
6.
7.
8.
9.
相關(guān)PDF資料
PDF描述
GS882Z36B-66I 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS882Z36B-80 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS882Z36B-80I 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS9000C Serial Digital Decoder
GS9000CCPJ Serial Digital Decoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS882Z36BD-250I V 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 165FPBGA - Trays
GS882Z36CB-200V 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 6.5NS/3NS 119FPBGA - Trays
GS882Z36CB-250V 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 119FPBGA - Trays
GS882Z36CB-300 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 119FPBGA - Trays
GS882Z36CD-200I 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*