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參數(shù)資料
| 型號(hào)： | GS882Z36B-80I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 8MB的流水線和流量，通過(guò)同步唑靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/34頁(yè) |
| 文件大?。?/td> | 802K |
| 代理商： | GS882Z36B-80I |
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Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
5/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
BPR2000.002.14
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.
U2
U3
U5
U4
TMS
TDI
TDO
TCK
V
DD
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
O
I
J2, C4, J4, R4, J6
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
GS882Z18/36 BGA Pin Description
Pin Location
Symbol
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9000C | Serial Digital Decoder |
| GS9000CCPJ | Serial Digital Decoder |
| GS9000CCTJ | Serial Digital Decoder |
| GS9001 | EDH COPROCESSOR |
| GS9001-CQM | EDH COPROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS882Z36BD-250I V | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 165FPBGA - Trays |
| GS882Z36CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 6.5NS/3NS 119FPBGA - Trays |
| GS882Z36CB-250V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 119FPBGA - Trays |
| GS882Z36CB-300 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 119FPBGA - Trays |
| GS882Z36CD-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
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